Abstract: A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated with fabricating a CMOS structure containing silicide contacts and silicide gate metals.

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

Abstract: A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface.

Abstract: A method is provided for fabricating a single-metal or dual metal replacement gate structure for a semiconductor device; the structure includes a silicide contact to the gate region. A dummy gate structure and sacrificial gate dielectric are removed to expose a portion of the substrate; a gate dielectric is formed thereon. A metal layer is formed overlying the gate dielectric and the dielectric material. This metal layer may conveniently be a blanket metal layer covering a device wafer. A silicon layer is then formed overlying the metal layer; this layer may also be a blanket wafer. A planarization or etchback process is then performed, so that the top surface of the dielectric material is exposed while other portions of the metal layer and the silicon layer remain in the gate region and have surfaces coplanar with the top surface of the dielectric material. A silicide contact is then formed which is in contact with the metal layer in the gate region.

Abstract: A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated in fabricating a CMOS structure containing silicide contacts and silicide gate metals.

Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

Abstract: A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.

Abstract: A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.

Abstract: A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.

Abstract: A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.

Abstract: A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 &mgr;m electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.

Abstract: A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.

Abstract: An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize the overlap capacitance in the device. The RSD construction uses a selective epitaxial process to effectively reduce the drain-source resistance. This improvement is even more significant in thin-film SOI technology. Using an RSD, the film outside the channel area thickens which, in turn, reduces the parasitic resistance.

Abstract: An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize the overlap capacitance in the device. The RSD construction uses a selective epitaxial process to effectively reduce the drain-source resistance. This improvement is even more significant in thin-film SOI technology. Using an RSD, the film outside the channel area thickens which, in turn, reduces the parasitic resistance.

Abstract: A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 &mgr;m electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.

Abstract: A notched gate MOS device includes either an encapsulated low dielectric material or encapsulated air or a vacuum at the bottom of a notched gate. Due to the low dielectric constant at the site of interface between the gate and the source/drain, the capacitance loss at that site is significantly reduced.

Abstract: A notched gate MOS device includes either an encapsulated low dielectric material or encapsulated air or a vacuum at the bottom of a notched gate. Due to the low dielectric constant at the site of interface between the gate and the source/drain, the capacitance loss at that site is significantly reduced.

Abstract: A method is provided for reducing contact resistances in semiconductors. In the use of fluorocarbon plasmas during high selectively sub-quarter-micron contact hole etching, with the silicon dioxide(SiO2)/silicon nitride(Si3N4)/silicide(TiSix) layers, polymerization effects have been discovered to be crucial. The process includes using a high etch selective chemistry, to remove SiO2 first, then switching to another chemistry with high selectivity of Si3N4-to-TiSix. To obtain good etch selectivity of SiO2-to-Si3Nx, fluorocarbon plasmas containing high C/F ratio are employed. This results in the information of reactive unsaturated polymers which stick easily to contact sidewalls and bottoms. Fluorine from the polymer was discovered to severely degrade the etch selectivity of Si3N4-to-TiSix. Different polymer removing methods to restore etch selectivity of Si3N4-to-TiSix, are provided which can be applied to any highly selective etching of oxide versus nitride.

Abstract: A method is provided for reducing contact resistances in semiconductors. In the use of fluorocarbon plasmas during high selectively sub-quarter-micron contact hole etching, with the silicon dioxide(SiO2)/silicon nitride(Si3N4)/silicide(TiSix) layers, polymerization effects have been discovered to be crucial. The process includes using a high etch selective chemistry, to remove SiO2 first, then switching to another chemistry with high selectivity of Si3N4-to-TiSix. To obtain good etch selectivity of SiO2-to-Si3N4, fluorocarbon plasmas containing high C/F ratio are employed. This results in the formation of reactive unsaturated polymers which stick easily to contact hole sidewalls and bottoms. Fluorine from the polymer was discovered to severely degrade the etch selectivity of Si3N4-to-TiSix. Different polymer removing methods to restore etch selectivity of Si3N4-to-TiSix are provided which can be applied to any highly selective etching of oxide versus nitride.