Patents by Inventor Victor Odisho
Victor Odisho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10908657Abstract: Described herein are baffles for Input/Output (I/O) devices and I/O devices comprising baffles configured to redirect incoming pre-heated air around downstream electrical components and/or their respective heat sinks to prevent overheating. Providing an isolated fresh airflow path from a fluid inlet to such downstream electrical devices reducing such overheating, which prevents malfunctions and increases the I/O efficiency, speed, and lifetime of I/O devices.Type: GrantFiled: February 15, 2019Date of Patent: February 2, 2021Assignee: PENSANDO SYSTEMS INC.Inventors: Victor Odisho, Lin Shen
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Publication number: 20200264678Abstract: Described herein are baffles for Input/Output (I/O) devices and I/O devices comprising baffles configured to redirect incoming pre-heated air around downstream electrical components and/or their respective heat sinks to prevent overheating. Providing an isolated fresh airflow path from a fluid inlet to such downstream electrical devices reducing such overheating, which prevents malfunctions and increases the I/O efficiency, speed, and lifetime of I/O devices.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Victor ODISHO, Lin SHEN
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Patent number: 10491701Abstract: An embodiment includes a first server including a first processor electrically connected to a second processor; a second server including a third processor electrically connected to a fourth processor; a first connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a first connection via the first connection plane and one of the first and second processors is connected to one of the third and fourth processors by a second connection via the first connection plane; and a second connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a third connection via the second connection plane and wherein one of the first and second processors is connected to one of the third and fourth processors by a fourth connection via the second connection plane.Type: GrantFiled: July 14, 2016Date of Patent: November 26, 2019Assignee: CISCO TECHNOLOGY, INC.Inventors: Victor Odisho, Bidyut Kanti Sen, Jayaprakash Balachandran, Michael Leung
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Publication number: 20180019953Abstract: An embodiment includes a first server including a first processor electrically connected to a second processor; a second server including a third processor electrically connected to a fourth processor; a first connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a first connection via the first connection plane and one of the first and second processors is connected to one of the third and fourth processors by a second connection via the first connection plane; and a second connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a third connection via the second connection plane and wherein one of the first and second processors is connected to one of the third and fourth processors by a fourth connection via the second connection plane.Type: ApplicationFiled: July 14, 2016Publication date: January 18, 2018Applicant: CISCO TECHNOLOGY, INC.Inventors: Victor Odisho, Bidyut Kanti Sen, Jayaprakash Balachandran, Michael Leung
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Patent number: 8727793Abstract: A small form-factor pluggable (SFP) module includes a board with an end portion to be inserted into a connector device. A first set of signal pads is arranged along an edge of a first surface of the SFP board at the end portion and a second set of signal pads along an edge of a second surface of the SFP board at the end portion. A third set of signal pads is disposed on the second surface at the end portion, offset from the edge of the second surface. A transceiver, coupled to the signal pads of the first, second, and third sets of signal pads, is configured to transmit and receive signals via the third set of signal pads and to transmit and receive signals via at least one of the first and second sets of signal pads.Type: GrantFiled: March 11, 2011Date of Patent: May 20, 2014Assignee: Cisco Technology, Inc.Inventors: Luca Cafiero, Zhiping Yang, Victor Odisho, Francisco Matus
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Publication number: 20120230700Abstract: A small form-factor pluggable (SFP) module includes a board with an end portion to be inserted into a connector device. A first set of signal pads is arranged along an edge of a first surface of the SFP board at the end portion and a second set of signal pads along an edge of a second surface of the SFP board at the end portion. A third set of signal pads is disposed on the second surface at the end portion, offset from the edge of the second surface. A transceiver, coupled to the signal pads of the first, second, and third sets of signal pads, is configured to transmit and receive signals via the third set of signal pads and to transmit and receive signals via at least one of the first and second sets of signal pads.Type: ApplicationFiled: March 11, 2011Publication date: September 13, 2012Applicant: CISCO TECHNOLOGY, INC.Inventors: Luca Cafiero, Zhiping Yang, Victor Odisho, Francisco Matus
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Patent number: 6520805Abstract: A memory module with offset notches for improved insertion and a memory module connector for mating thereto. The connector housing includes an accommodating s space for receiving a portion of the memory module printed circuit board (PCB). A first key is disposed within the accommodating space of the housing and is positioned between the first end and the center of the housing. A second key is flirter disposed within the accommodating space and is positioned between the second end of the housing and the center. A distance between the first key and the second key is greater than 40% of the length of the housing. Either the first, second, or both keys may extend from the accommodating space beyond a top plane defined by a top side of the accommodating space of the housing. The memory module comprises the PCB with a first notch positioned between the first end of the PCB and the center of the PCB. A second notch is positioned between the second end of the PCB and the center of the PCB.Type: GrantFiled: October 3, 2001Date of Patent: February 18, 2003Assignee: Sun Microsystems, Inc.Inventors: Ali Hassanzadeh, Victor Odisho
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Patent number: 6428360Abstract: A memory module with offset notches for improved insertion and a memory module connector for mating thereto. The connector housing includes an accommodating space for receiving a portion of the memory module printed circuit board (PCB). A first key is disposed within the accommodating space of the housing and is positioned between the first end and the center of the housing. A second key is further disposed within the accommodating space and is positioned between the second end of the housing and the center. A distance between the first key and the second key is greater than 40% of the length of the housing. Either the first, second, or both keys may extend from the accommodating space beyond a top plane defined by a top side of the accommodating space of the housing. The memory module comprises the PCB with a first notch positioned between the first end of the PCB and the center of the PCB. A second notch is positioned between the second end of the PCB and the center of the PCB.Type: GrantFiled: January 4, 2001Date of Patent: August 6, 2002Assignee: Sun Microsystems, Inc.Inventors: Ali Hassanzadeh, Victor Odisho
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Publication number: 20020019170Abstract: A memory module with offset notches for improved insertion and a memory module connector for mating thereto. The connector housing includes an accommodating s space for receiving a portion of the memory module printed circuit board (PCB). A first key is disposed within the accommodating space of the housing and is positioned between the first end and the center of the housing. A second key is flirter disposed within the accommodating space and is positioned between the second end of the housing and the center. A distance between the first key and the second key is greater than 40% of the length of the housing. Either the first, second, or both keys may extend from the accommodating space beyond a top plane defined by a top side of the accommodating space of the housing. The memory module comprises the PCB with a first notch positioned between the first end of the PCB and the center of the PCB. A second notch is positioned between the second end of the PCB and the center of the PCB.Type: ApplicationFiled: October 3, 2001Publication date: February 14, 2002Applicant: Sun Microsystems, IncInventors: Ali Hassanzadeh, Victor Odisho
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Patent number: 6315614Abstract: A memory module with offset notches for improved insertion and a memory module connector for mating thereto. The connector housing includes an accommodating space for receiving a portion of the memory module printed circuit board (PCB). A first key is disposed within the accommodating space of the housing and is positioned between the first end and the center of the housing. A second key is further disposed within the accommodating space and is positioned between the second end of the housing and the center. A distance between the first key and the second key is greater than 40% of the length of the housing for stability of the memory module while encased by the housing. Either the first, second, or both keys may extend from the accommodating space beyond a top plane defined by a top side of the accommodating space of the housing. The memory module comprises the PCB with a first notch positioned between the first end of the PCB and the center of the PCB.Type: GrantFiled: April 16, 1999Date of Patent: November 13, 2001Assignee: Sun Microsystems, Inc.Inventors: Ali Hassanzadeh, Victor Odisho
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Publication number: 20010001085Abstract: A memory module with offset notches for improved insertion and a memory module connector for mating thereto. The connector housing includes an accommodating space for receiving a portion of the memory module printed circuit board (PCB). A first key is disposed within the accommodating space of the housing and is positioned between the first end and the center of the housing. A second key is further disposed within the accommodating space and is positioned between the second end of the housing and the center. A distance between the first key and the second key is greater than 40% of the length of the housing. Either the first, second, or both keys may extend from the accommodating space beyond a top plane defined by a top side of the accommodating space of the housing. The memory module comprises the PCB with a first notch positioned between the first end of the PCB and the center of the PCB. A second notch is positioned between the second end of the PCB and the center of the PCB.Type: ApplicationFiled: January 4, 2001Publication date: May 10, 2001Inventors: Ali Hassanzadeh, Victor Odisho
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Patent number: 5790890Abstract: An identification interface that transfers control information between a controller and an option module coupled to a motherboard of a computer. The identification interface supports the propagation of a plurality of bit fields containing information pertaining to the characteristics of the option module including, but not limited to, its speed, type and other information about its characteristics.Type: GrantFiled: February 29, 1996Date of Patent: August 4, 1998Assignee: Sun Microsystems, Inc.Inventors: Russell N. Mirov, Victor Odisho
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Patent number: 5758100Abstract: A component card interconnect apparatus for coupling a component card to a computer system. A component card includes a first group of in-line pins with first power pins for conveying a first voltage and a second group of in-line pins with second power pins for conveying a second voltage. The second voltage is lower than the first voltage. Either the first or the second voltage is conveyed at one time.Type: GrantFiled: July 1, 1996Date of Patent: May 26, 1998Assignee: Sun Microsystems, Inc.Inventor: Victor Odisho