Patents by Inventor Victor Paul Seidel

Victor Paul Seidel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Field programmable memory array
    Patent number: 6075745
    Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: June 13, 2000
    Assignee: International Business Machines Corporation
    Inventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch
  • Memory cells for field programmable memory array
    Patent number: 6038192
    Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: March 14, 2000
    Assignee: International Business Machines Corporation
    Inventors: Kim P. N. Clinton, Joseph Andrew Iadanza, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch
  • Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array
    Patent number: 6023421
    Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: February 8, 2000
    Assignee: International Business Machines Corporation
    Inventors: Kim P. N. Clinton, Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
  • Field programmable memory array
    Patent number: 5949719
    Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: September 7, 1999
    Assignee: International Business Machines Corporation
    Inventors: Kim P. N. Clinton, Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
  • Field programmable memory array
    Patent number: 5914906
    Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: June 22, 1999
    Assignee: International Business Machines Corporation
    Inventors: Joseph Andrew Iadanza, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch