Patents by Inventor Victor W. Lee

Victor W. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7484014
    Abstract: A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: January 27, 2009
    Assignee: Intel Corporation
    Inventors: K. Phanindra Mannava, Victor W. Lee, Aaron T. Spink
  • Patent number: 7350036
    Abstract: A technique to perform concurrent updates to a shared data structure. At least one embodiment of the invention concurrently stores copies of a data structure within a plurality of local caches, updates the local caches with a partial result of a computation distributed among a plurality of processing elements, and returns the partial results to combining logic in parallel, which combines the partial results into a final result.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Daehyun Kim, Victor W. Lee, Anthony D. Nguyen, Mikhail Smelyanskiy
  • Patent number: 7328368
    Abstract: In some embodiments an apparatus includes a transmission error detector to detect an error of a transmission of an interconnect and a transmitting agent to retry the transmission in response to the detected error. The apparatus also includes a hard failure detector to detect a hard failure of the interconnect if the retry is unsuccessful, and a transmission width reducer to reduce a transmission width of the interconnect in response to the hard failure detector. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventors: Phanindra K. Mannava, Victor W. Lee, Akhilesh Kumar, Doddaballapur N. Jayasimha, Ioannis T. Schoinas
  • Patent number: 7320094
    Abstract: Systems and methods of retraining a receiver provide for determining a minimum transition density for a derived clock data link to the receiver. A retraining flit is generated based on the minimum transition density. In one approach, the retraining flit is generated by defining control data and payload data for the retraining flit. Error detection data is determined for the retraining flit based on the control and the payload data. The control data, the payload data and the error detection data have sufficient transitions to meet the minimum transition density.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: January 15, 2008
    Assignee: Intel Corporation
    Inventors: Victor W. Lee, Phanindra K. Mannava, Akhilesh Kumar, Sanjay Dabral
  • Patent number: 6976311
    Abstract: An apparatus is provided comprising a first knife and a second knife. The first knife typically includes a first attachment device and the second knife includes a second attachment device to attach the two knives together. The first and second attachment devices can be detached to detach the two knives from each other. The first and second knives can be folding type knives. The first attachment device may be comprised of a first plate having an opening. The second attachment device may be comprised of a protrusion. The protrusion of the second attachment device can be inserted into the opening of the first plate to attach the first knife to the second knife.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: December 20, 2005
    Inventor: Victor W. Lee
  • Patent number: 6975954
    Abstract: A method of testing a DUT is provided. The method comprises loading a memory within a link-based system with a functional test program, executing the functional test program in a processor core of the link-based system, and routing test signals generated during execution of the functional test program to a response agent embedded in the link-based system via an external path.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Tak M. Mak, Victor W. Lee
  • Publication number: 20040267484
    Abstract: A method is provided. The method comprises loading a memory within a link-based system with a functional test program, executing the functional test program in a processor core of the link-based system, and routing test signals generated during execution of the functional test program to a response agent embedded in the link-based system via an external path.
    Type: Application
    Filed: June 24, 2003
    Publication date: December 30, 2004
    Inventors: Tak M. Mak, Victor W. Lee
  • Publication number: 20040204519
    Abstract: A chlorinated resin or chlorinated paraffin wax coupling agent is disclosed for enhancing the physical properties while simultaneously lowering the melt viscosity during extrusion of a cellulose-filled thermoplastic polymer composite.
    Type: Application
    Filed: March 29, 2004
    Publication date: October 14, 2004
    Inventors: W. Matthew Fender, Tom Kelley, Victor W. Lee
  • Publication number: 20040193986
    Abstract: An apparatus and method for generating test patterns with an on-die self test circuit (e.g., IBIST) are disclosed. In various embodiments, the IBIST comprises a sub-pattern generator that may include one or more of a storage element for a user-defined sub-pattern, a clock sub-pattern generator, and a constant sub-pattern generator. A multiplexer is used to assemble a test pattern based on a combination of sub-patterns from the sub-pattern generator.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Inventors: Karthisha S. Canagasaby, Victor W. Lee, Jay J. Nejedlo
  • Publication number: 20030233601
    Abstract: Internal bus observation techniques for an electronic module or integrated circuit. In one embodiment, a disclosed apparatus includes observation logic to observe an observed bus and a debug buffer. The observation logic captures a record reflecting signal observed on the observed bus. The debug buffer is coupled to the observation logic to receive the record that reflects signal observed by the observation logic. The debug buffer generates a transaction to transfer the record to a storage device to store the record.
    Type: Application
    Filed: June 17, 2002
    Publication date: December 18, 2003
    Inventors: Kushagra V. Vaid, Piyush Desai, Victor W. Lee
  • Publication number: 20030030040
    Abstract: Disclosed are a reversibly variable color patterning composition for articles made of synthetic resin that include a granulated material containing 1.) at least one reversibly variable photochromic material which is any one of the following or any combination of the following: encapsulated, microencapsulated, or non-encapsulated photochromic dye and 2.) an olefin polymer, copolymer, or terpolymer, the granulated materials not having been subject to a crosslinking reaction.
    Type: Application
    Filed: August 8, 2001
    Publication date: February 13, 2003
    Inventors: John Joseph Luthern, Victor W. Lee
  • Patent number: 6162851
    Abstract: A highly flame retardant, impact modified polyolefin alloy is described, the composition of which includes: at least one polyolefin; at least one halogenated organic flame retardant; at least one semi-crystalline ethylene copolymer impact modifier, the copolymer optionally being functionalized, at least one oxygen-containing metal compound wherein the metal is selected from the group consisting of Group III, IV, V, and VI of the Periodic Table; and at least one fluorocarbon, at least a portion of which is fibrillated or fibrillatable. Optionally, the alloy will contain at least one of a functionalized silicone polymer, a hydrated metal silicate, a hydrated metal borate, a primary antioxidant, and a secondary antioxidant. Such thermoplastic polymer blends/alloys can be produced by combining all ingredients in a melt and applying shear to the melt through means of a high shear internal/continuous mixer or an extruder.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: December 19, 2000
    Assignee: ICC Industries Inc.
    Inventors: Michael T. Wood, Steven D. Landau, Victor W. Lee, Ralph E. WyKoff
  • Patent number: 4592861
    Abstract: An antistatic thermoplastic composition comprising a blend of a thermoplastic graft polymer; a thermoplastic halogenated polymer; and an amount of conductive carbon black effective to cause the composition to have a surface resistivity of 10.sup.2 -10.sup.12 ohm/square, wherein the ratio of (a)/(b) is from 9:1-1:9, by weight and the weight percentage of (c) is from 2-10%.
    Type: Grant
    Filed: June 8, 1984
    Date of Patent: June 3, 1986
    Assignee: Uniroyal Chemical Company, Inc.
    Inventors: Solomon Bekele, Victor W. Lee