Patents by Inventor Victor Zyuban
Victor Zyuban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063715Abstract: A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Inventors: Alexander B. Uan-Zo-li, Shuai Jiang, Jamie L. Langlinais, Per H. Hammarlund, Hans L. Yeager, Victor Zyuban, Sung J. Kim, Wei Xu, Rohan U. Mandrekar, Sambasivan Narayan, Mohamed H. Abu-Rahma, Jaroslav Raszka, Robert O. Bruckner
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Patent number: 11722060Abstract: A converter circuit, included in a power converter circuit, may generate a given voltage level on a regulated power supply node of a computer system. A control circuit may monitor a voltage level and assert a control signal in response to a determination that a regulation event has occurred. A boost converter circuit, included in the power converter circuit, may inject charge into to the regulated power supply node via a capacitor, in response to an assertion of the control signal.Type: GrantFiled: July 22, 2020Date of Patent: August 8, 2023Assignee: Apple Inc.Inventors: Victor Zyuban, Norman J. Rohrer, Shawn Searles
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Patent number: 11675380Abstract: A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.Type: GrantFiled: April 7, 2022Date of Patent: June 13, 2023Assignee: Apple Inc.Inventors: Shawn Searles, Victor Zyuban, Mohamed Abu-Rahma
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Publication number: 20220300022Abstract: A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.Type: ApplicationFiled: April 7, 2022Publication date: September 22, 2022Inventors: Shawn Searles, Victor Zyuban, Mohamed Abu-Rahma
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Patent number: 11418174Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.Type: GrantFiled: April 30, 2021Date of Patent: August 16, 2022Assignee: Apple Inc.Inventors: Greg M. Hess, Vivekanandan Venugopal, Victor Zyuban
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Patent number: 11418194Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.Type: GrantFiled: August 11, 2021Date of Patent: August 16, 2022Assignee: Apple Inc.Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
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Patent number: 11320849Abstract: A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.Type: GrantFiled: August 28, 2020Date of Patent: May 3, 2022Assignee: Apple Inc.Inventors: Shawn Searles, Victor Zyuban, Mohamed Abu-Rahma
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Publication number: 20220066490Abstract: A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Shawn Searles, Victor Zyuban, Mohamed Abu-Rahma
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Publication number: 20220029536Abstract: A converter circuit, included in a power converter circuit, may generate a given voltage level on a regulated power supply node of a computer system. A control circuit may monitor a voltage level and assert a control signal in response to a determination that a regulation event has occurred. A boost converter circuit, included in the power converter circuit, may inject charge into to the regulated power supply node via a capacitor, in response to an assertion of the control signal.Type: ApplicationFiled: July 22, 2020Publication date: January 27, 2022Inventors: Victor Zyuban, Norman J. Rohrer, Shawn Searles
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Publication number: 20210376831Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.Type: ApplicationFiled: August 11, 2021Publication date: December 2, 2021Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
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Patent number: 11152046Abstract: A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.Type: GrantFiled: July 17, 2020Date of Patent: October 19, 2021Assignee: Apple Inc.Inventors: Jaroslav Raszka, Shahzad Nazar, Jaemyung Lim, Mohamed H. Abu-Rahma, Victor Zyuban
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Patent number: 11121711Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.Type: GrantFiled: August 31, 2020Date of Patent: September 14, 2021Assignee: Apple Inc.Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
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Publication number: 20210250019Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.Type: ApplicationFiled: April 30, 2021Publication date: August 12, 2021Inventors: Greg M. Hess, Vivekanandan Venugopal, Victor Zyuban
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Patent number: 11005459Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.Type: GrantFiled: April 22, 2019Date of Patent: May 11, 2021Assignee: Apple Inc.Inventors: Greg M. Hess, Vivekanandan Venugopal, Victor Zyuban
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Patent number: 10908663Abstract: A power switch multiplexer with configurable overlap is disclosed. An integrated circuit (IC) includes a first functional circuit block coupled to receive a supply voltage from a first supply voltage node. The IC further includes an input circuit and an output circuit. Responsive to receiving an input signal, the input circuit asserts an activation signal to cause one of a second supply voltage node and a third supply voltage node to be electrically coupled to the first supply voltage node. Subsequently the input circuit asserts a deactivation signal to cause the other one of the second and third supply voltage nodes to be electrically decoupled from the first supply voltage node. The output circuit is coupled to receive the activation signal and the deactivation signal, and configured to assert a first output signal subsequent to receiving the activation signal.Type: GrantFiled: June 6, 2019Date of Patent: February 2, 2021Assignee: Apple Inc.Inventors: Victor Zyuban, Greg M. Hess, Hemangi U. Gajjewar
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Publication number: 20210028785Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.Type: ApplicationFiled: August 31, 2020Publication date: January 28, 2021Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
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Publication number: 20200387205Abstract: A power switch multiplexer with configurable overlap is disclosed. An integrated circuit (IC) includes a first functional circuit block coupled to receive a supply voltage from a first supply voltage node. The IC further includes an input circuit and an output circuit. Responsive to receiving an input signal, the input circuit asserts an activation signal to cause one of a second supply voltage node and a third supply voltage node to be electrically coupled to the first supply voltage node. Subsequently the input circuit asserts a deactivation signal to cause the other one of the second and third supply voltage nodes to be electrically decoupled from the first supply voltage node. The output circuit is coupled to receive the activation signal and the deactivation signal, and configured to assert a first output signal subsequent to receiving the activation signal.Type: ApplicationFiled: June 6, 2019Publication date: December 10, 2020Inventors: Victor Zyuban, Greg M. Hess, Hemangi U. Gajjewar
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Patent number: 10763859Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.Type: GrantFiled: November 18, 2019Date of Patent: September 1, 2020Assignee: Apple Inc.Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
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Publication number: 20200162077Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.Type: ApplicationFiled: November 18, 2019Publication date: May 21, 2020Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
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Patent number: 10599207Abstract: A method and apparatus for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for the inhibited processor cores, and then uninhibiting the processor cores requesting exit from the idle state.Type: GrantFiled: December 7, 2017Date of Patent: March 24, 2020Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Guillermo J. Silva, Gregory S. Still, Victor Zyuban