Patents by Inventor Vidura Manu Wijayasekara

Vidura Manu Wijayasekara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Self-timed processors implemented with multi-rail null convention logic and unate gates
    Patent number: 10951212
    Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: March 16, 2021
    Assignee: Eta Compute, Inc.
    Inventors: Chao Xu, Gopal Raghavan, Ben Wiley Melton, Vidura Manu Wijayasekara, Bryan Garnett Cope, David Cureton Baker, John Whitaker Havlicek
  • Interface from null convention logic to synchronous memory
    Patent number: 10642759
    Abstract: Self-timed processing systems and methods of operating self-timed processing systems are disclosed. A self-timed processing system includes an asynchronous null convention logic (NCL) processor, a memory that accepts input signals on an active edge of a memory clock signal, and logic to combine a first acknowledge signal and a second acknowledge signal to generate the memory clock signal. The first acknowledge signal indicates input signals are ready to be accepted by the memory. The second acknowledge signal indicates data signals previously output from the memory have been accepted by the processor.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: May 5, 2020
    Assignee: Eta Compute, Inc.
    Inventors: Vidura Manu Wijayasekara, Ben Wiley Melton, Bryan Garnett Cope
  • SELF-TIMED PROCESSORS IMPLEMENTED WITH MULTI-RAIL NULL CONVENTION LOGIC AND UNATE GATES
    Publication number: 20190190520
    Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.
    Type: Application
    Filed: February 7, 2019
    Publication date: June 20, 2019
    Inventors: Chao Xu, Gopal Raghavan, Ben Wiley Melton, Vidura Manu Wijayasekara, Bryan Garnett Cope, David Cureton Baker, John Whitaker Havlicek
  • Self-timed processors implemented with multi-rail null convention logic and unate gates
    Patent number: 10205453
    Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: February 12, 2019
    Assignee: Eta Compute, Inc.
    Inventors: Chao Xu, Gopal Raghavan, Ben Wiley Melton, Vidura Manu Wijayasekara, Bryan Garnett Cope, David Cureton Baker, John Whitaker Havlicek
  • INTERFACE FROM NULL CONVENTION LOGIC TO SYNCHRONOUS MEMORY
    Publication number: 20180300263
    Abstract: Self-timed processing systems and methods of operating self-timed processing systems are disclosed. A self-timed processing system includes an asynchronous null convention logic (NCL) processor, a memory that accepts input signals on an active edge of a memory clock signal, and logic to combine a first acknowledge signal and a second acknowledge signal to generate the memory clock signal. The first acknowledge signal indicates input signals are ready to be accepted by the memory. The second acknowledge signal indicates data signals previously output from the memory have been accepted by the processor.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 18, 2018
    Inventors: Vidura Manu Wijayasekara, Ben Wiley Melton, Bryan Garnett Cope
  • SELF-TIMED PROCESSORS IMPLEMENTED WITH MULTI-RAIL NULL CONVENTION LOGIC AND UNATE GATES
    Publication number: 20180294810
    Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 11, 2018
    Inventors: Chao Xu, Gopal Raghavan, Ben Wiley Melton, Vidura Manu Wijayasekara, Bryan Garnett Cope, David Cureton Baker, John Whitaker Havlicek