Patents by Inventor Vidyadhara Bellippady

Vidyadhara Bellippady has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-volatile two-transistor programmable logic cell and array layout
    Patent number: 7285818
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: October 23, 2007
    Assignee: Actel Corporation
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang
  • NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
    Publication number: 20070215935
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Application
    Filed: May 18, 2007
    Publication date: September 20, 2007
    Applicant: ACTEL CORPORATION
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang
  • Non-volatile two-transistor programmable logic cell and array layout
    Publication number: 20060284238
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang