Patents by Inventor VietHa NGUYEN
VietHa NGUYEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10916437Abstract: Provided herein is a method of forming micropatterns, including: forming an etching target film on a substrate; forming a photosensitivity assisting layer on the etching target film, the photosensitivity assisting layer being terminated with a hydrophilic group; forming an adhesive layer on the photosensitivity assisting layer, the adhesive layer forming a covalent bond with the hydrophilic group; forming a hydrophobic photoresist film on the adhesive layer; and patterning the photoresist film.Type: GrantFiled: December 27, 2018Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Shin Jang, Jong-Min Baek, Hoon-Seok Seo, Eui-Bok Lee, Sung-Jin Kang, Vietha Nguyen, Deok-Young Jung, Sang-Hoon Ahn, Hyeok-Sang Oh, Woo-Kyung You
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Publication number: 20190198342Abstract: Provided herein is a method of forming micropatterns, including: forming an etching target film on a substrate; forming a photosensitivity assisting layer on the etching target film, the photosensitivity assisting layer being terminated with a hydrophilic group; forming an adhesive layer on the photosensitivity assisting layer, the adhesive layer forming a covalent bond with the hydrophilic group; forming a hydrophobic photoresist film on the adhesive layer; and patterning the photoresist film.Type: ApplicationFiled: December 27, 2018Publication date: June 27, 2019Inventors: SANG-SHIN JANG, JONG-MIN BAEK, HOON-SEOK SEO, EUI-BOK LEE, SUNG-JIN KANG, VIETHA NGUYEN, DEOK-YOUNG JUNG, SANG-HOON AHN, HYEOK-SANG OH, WOO-KYUNG YOU
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Patent number: 10304734Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.Type: GrantFiled: July 26, 2018Date of Patent: May 28, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Kyung You, Jong Min Baek, Sang Shin Jang, Byung Hee Kim, Vietha Nguyen, Nae In Lee, Woo Jin Lee, Eun Ji Jung, Kyu Hee Han
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Patent number: 10192782Abstract: A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.Type: GrantFiled: June 23, 2015Date of Patent: January 29, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Woojin Lee, VietHa Nguyen, Wookyung You, Doo-Sung Yun, Hyunbae Lee, Byunghee Kim, Sang Hoon Ahn, Seungyong Yoo, Naein Lee, Hoyun Jeon
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Patent number: 10186485Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.Type: GrantFiled: February 15, 2018Date of Patent: January 22, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
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Publication number: 20180330987Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.Type: ApplicationFiled: July 26, 2018Publication date: November 15, 2018Inventors: WOO KYUNG YOU, JONG MIN BAEK, SANG SHIN JANG, BYUNG HEE KIM, VIETHA NGUYEN, NAE IN LEE, WOO JIN LEE, EUN JI JUNG, KYU HEE HAN
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Patent number: 10090381Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.Type: GrantFiled: June 21, 2017Date of Patent: October 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongmin Baek, Vietha Nguyen, Wookyung You, Sangshin Jang, Byunghee Kim, Kyu-Hee Han
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Patent number: 10062609Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.Type: GrantFiled: December 29, 2016Date of Patent: August 28, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Kyung You, Jong Min Baek, Sang Shin Jang, Byung Hee Kim, Vietha Nguyen, Nae In Lee, Woo Jin Lee, Eun Ji Jung, Kyu Hee Han
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Publication number: 20180174977Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
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Patent number: 9972528Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.Type: GrantFiled: December 9, 2016Date of Patent: May 15, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: VietHa Nguyen, Thomas Oszinda, Jongmin Baek, Sanghoon Ahn, Byunghee Kim, Wookyung You, Naein Lee
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Patent number: 9929099Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.Type: GrantFiled: November 21, 2016Date of Patent: March 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
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Publication number: 20180083099Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.Type: ApplicationFiled: June 21, 2017Publication date: March 22, 2018Inventors: JONGMIN BAEK, VIETHA NGUYEN, WOOKYUNG YOU, Sangshin JANG, BYUNGHEE KIM, Kyu-Hee HAN
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Publication number: 20180033691Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.Type: ApplicationFiled: December 29, 2016Publication date: February 1, 2018Inventors: Woo Kyung You, JONG MIN BAEK, SANG SHIN JANG, BYUNG HEE KIM, VIETHA NGUYEN, NAE IN LEE, WOO JIN LEE, EUN JI JUNG, KYU HEE HAN
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Publication number: 20170178949Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.Type: ApplicationFiled: December 9, 2016Publication date: June 22, 2017Inventors: VietHa Nguyen, Thomas Oszinda, Jongmin Baek, Sanghoon Ahn, Byunghee Kim, Wookyung You, Naein Lee
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Publication number: 20170170184Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.Type: ApplicationFiled: November 21, 2016Publication date: June 15, 2017Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
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Publication number: 20160133512Abstract: A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.Type: ApplicationFiled: June 23, 2015Publication date: May 12, 2016Inventors: Woojin LEE, VietHa NGUYEN, Wookyung YOU, Doo-Sung YUN, Hyunbae LEE, Byunghee KIM, Sang Hoon AHN, Seungyong YOO, Naein LEE, Hoyun JEON