Patents by Inventor Vignesh Trichy Ravi

Vignesh Trichy Ravi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11799738
    Abstract: A system, method, and apparatus may provide one or more tangible, nontransitory computer-readable storage media having stored thereon executable instructions to instruct a processor to: stripe an outgoing network message into two or more pieces; send a first piece to a receiver via a first network interface card (NIC), and a second piece to the receiver via a second NIC; and upon determining that the receiver failed to receive a piece of the outgoing network message, replay the piece that the receiver failed to receive via a third NIC.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: October 24, 2023
    Assignee: Intel Corporation
    Inventors: Ravindra Babu Ganapathi, Andrew Friedley, Ravi Murty, Vignesh Trichy Ravi
  • Patent number: 11736402
    Abstract: There is included in one example a switch, including: an ingress port to receive data from a source host; a first egress port to send data to a destination host; a second egress port to send data to the source host; and a congestion notification generator (CNG) including: a congestion detector to compute bandwidth consumption of a flow associated with a packet received on the ingress port and assigned to the first egress port, and determine based on the computed bandwidth consumption that the flow is congested; a flow extractor to extract a flow identifier of the flow from the packet; a throttle calculator to calculate a quantitative flow throttle value for the flow; and a header builder to build a congestion notification packet to instruct the source host to throttle the flow.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Vignesh Trichy Ravi, Ravi Murty, Ravindra Babu Ganapathi, Michael A. Parker
  • Publication number: 20220141138
    Abstract: There is included in one example a switch, including: an ingress port to receive data from a source host; a first egress port to send data to a destination host; a second egress port to send data to the source host; and a congestion notification generator (CNG) including: a congestion detector to compute bandwidth consumption of a flow associated with a packet received on the ingress port and assigned to the first egress port, and determine based on the computed bandwidth consumption that the flow is congested; a flow extractor to extract a flow identifier of the flow from the packet; a throttle calculator to calculate a quantitative flow throttle value for the flow; and a header builder to build a congestion notification packet to instruct the source host to throttle the flow.
    Type: Application
    Filed: October 13, 2021
    Publication date: May 5, 2022
    Applicant: Intel Corporation
    Inventors: Vignesh Trichy Ravi, Ravi Murty, Ravindra Babu Ganapathi, Michael A. Parker
  • Publication number: 20220131768
    Abstract: A system, method, and apparatus may provide one or more tangible, nontransitory computer-readable storage media having stored thereon executable instructions to instruct a processor to: stripe an outgoing network message into two or more pieces; send a first piece to a receiver via a first network interface card (NIC), and a second piece to the receiver via a second NIC; and upon determining that the receiver failed to receive a piece of the outgoing network message, replay the piece that the receiver failed to receive via a third NIC.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: Intel Corporation
    Inventors: Ravindra Babu Ganapathi, Andrew Friedley, Ravi Murty, Vignesh Trichy Ravi
  • Patent number: 11277350
    Abstract: Particular embodiments described herein provide for a system for enabling the communication of a large message using multiple network interface controllers (NICs). The system can be configured to determine that a message to communicate to a receiver over a network is above a threshold, determine a plurality of NICs to be used to communicate the message, create a manifest that includes an identifier of each of the plurality of NICs, and communicate the manifest to the receiver using a multi-unit message. In an example, the multi-unit message is communicated using a PUT command and the receiver can analyze the manifest and use a GET command to pull the message from the plurality of NICs.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Murty, Keith D. Underwood, Ravindra Babu Ganapathi, Andrew Friedley, Vignesh Trichy Ravi
  • Patent number: 11153211
    Abstract: There is included in one example a switch, including: an ingress port to receive data from a source host; a first egress port to send data to a destination host; a second egress port to send data to the source host; and a congestion notification generator (CNG) including: a congestion detector to compute bandwidth consumption of a flow associated with a packet received on the ingress port and assigned to the first egress port, and determine based on the computed bandwidth consumption that the flow is congested; a flow extractor to extract a flow identifier of the flow from the packet; a throttle calculator to calculate a quantitative flow throttle value for the flow; and a header builder to build a congestion notification packet to instruct the source host to throttle the flow.
    Type: Grant
    Filed: December 9, 2017
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Vignesh Trichy Ravi, Ravi Murty, Ravindra Babu Ganapathi, Michael A. Parker
  • Publication number: 20190182161
    Abstract: There is included in one example a switch, including: an ingress port to receive data from a source host; a first egress port to send data to a destination host; a second egress port to send data to the source host; and a congestion notification generator (CNG) including: a congestion detector to compute bandwidth consumption of a flow associated with a packet received on the ingress port and assigned to the first egress port, and determine based on the computed bandwidth consumption that the flow is congested; a flow extractor to extract a flow identifier of the flow from the packet; a throttle calculator to calculate a quantitative flow throttle value for the flow; and a header builder to build a congestion notification packet to instruct the source host to throttle the flow.
    Type: Application
    Filed: December 9, 2017
    Publication date: June 13, 2019
    Applicant: Intel Corporation
    Inventors: Vignesh Trichy Ravi, Ravi Murty, Ravindra Babu Ganapathi, Michael A. Parker
  • Publication number: 20190044827
    Abstract: Particular embodiments described herein provide for a system for enabling the communication of a message using a network interface controller (NICs) on a subnet. In an example, the system is applicable to hardware offload NICs such as those implementing the Portals protocol. The system can be configured to determine a NIC in a first subnet to be used to communicate a message, where the NIC is configured to comply with a message passing interface protocol, create a manifest that includes an identifier of the NICs and a subnet ID that identifies the first subnet, and communicate the manifest to the receiver.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 7, 2019
    Applicant: INTEL CORPORATOIN
    Inventors: Ravindra Babu Ganapathi, Andrew Friedley, Ravi Murty, Vignesh Trichy Ravi
  • Publication number: 20190044875
    Abstract: Particular embodiments described herein provide for a system for enabling the communication of a large message using multiple network interface controllers (NICs). The system can be configured to determine that a message to communicate to a receiver over a network is above a threshold, determine a plurality of NICs to be used to communicate the message, create a manifest that includes an identifier of each of the plurality of NICs, and communicate the manifest to the receiver using a multi-unit message. In an example, the multi-unit message is communicated using a PUT command and the receiver can analyze the manifest and use a GET command to pull the message from the plurality of NICs.
    Type: Application
    Filed: January 9, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Ravi Murty, Keith D. Underwood, Ravindra Babu Ganapathi, Andrew Friedley, Vignesh Trichy Ravi
  • Patent number: 10025361
    Abstract: A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: July 17, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Indrani Paul, Vignesh Trichy Ravi, Manish Arora, Srilatha Manne
  • Patent number: 9261938
    Abstract: An apparatus and methods for controlling energy consumption of an electronic device determine an availability of an energy source to provide energy to the electronic device. The apparatus and methods control, by power management control logic of the electronic device, energy consumption of the electronic device in response to determining the availability of the energy source.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: February 16, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Manish Arora, Vignesh Trichy Ravi, Indrani Paul
  • Publication number: 20160018870
    Abstract: An apparatus and methods for controlling energy consumption of an electronic device determine an availability of an energy source to provide energy to the electronic device. The apparatus and methods control, by power management control logic of the electronic device, energy consumption of the electronic device in response to determining the availability of the energy source.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 21, 2016
    Inventors: Manish Arora, Vignesh Trichy Ravi, Indrani Paul
  • Publication number: 20150355692
    Abstract: A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Inventors: Indrani Paul, Vignesh Trichy Ravi, Manish Arora, Srilatha Manne
  • Publication number: 20150067356
    Abstract: A data processing system includes a plurality of processor resources, a manager, and a power distributor. Each of the plurality of data processor cores is operable at a selected one of a plurality of performance states. The manager assigns each of a plurality of program elements to one of the plurality of processor resources, and synchronizing the program elements using barriers. The power distributor is coupled to the manager and to the plurality of processor resources, and assigns a performance state to each of the plurality of processor resources within an overall power budget, and in response to detecting that a program element assigned to a first processor resource is at a barrier, increases the performance state of a second processor resource that is not at the barrier within the overall power budget.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vignesh Trichy Ravi, Manish Arora, William Brantley, Srilatha Manne, Indrani Paul, Michael Schulte