Patents by Inventor Vijai Sinha

Vijai Sinha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6554560
    Abstract: A wafer orienting apparatus for aligning a plurality of semiconductor wafers each of which has a v-notch formed on its outer periphery. The apparatus includes a cassette process carrier for supporting the plurality of wafers in parallel wafer supporting slots and wafer supporting means engaging the periphery of each wafer in an individual slot with the central axis of all wafers in coaxial alignment. A supporting platform is placed over the cassette for supporting the wafers in an inverted position in which the wafers are substantially vertical and biased by their own weight against a multiplicity of orienting mechanisms. The orienting mechanisms are arranged to correspond to each wafer position within the cassette. The plurality of orienting mechanisms are integrated with the supporting platform so that all wafers within the cassette can be aligned during this aligning process.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: April 29, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Vijai Sinha
  • Publication number: 20010038791
    Abstract: A wafer orienting apparatus for aligning a plurality of semiconductor wafers each of which has a v-notch formed on its outer periphery. The apparatus includes a cassette process carrier for supporting the plurality of wafers in parallel wafer supporting slots and wafer supporting means engaging the periphery of each wafer in an individual slot with the central axis of all wafers in coaxial alignment A supporting platform is placed over the cassette for supporting the wafers in an inverted position in which the wafers are substantially vertical and biased by their own weight against a multiplicity of orienting mechanisms. The orienting mechanisms are arranged to correspond to each wafer position within the cassette. The plurality of orienting mechanisms are integrated with the supporting platform so that all wafers within the cassette can be aligned during this aligning process.
    Type: Application
    Filed: July 16, 2001
    Publication date: November 8, 2001
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventor: Vijai Sinha
  • Patent number: 6270307
    Abstract: A wafer orienting apparatus for aligning a plurality of semiconductor wafers each of which bas a v-notch formed on its outer periphery. The apparatus includes a cassette process carrier for supporting the plurality of wafers in parallel wafer supporting slots and wafer support means engaging the periphery of each wafer in an individual slot with the central axis of all wafers in coaxial alignment. A supporting platform is placed over the cassette for supporting the wafers in an inverted position in which the wafers are substantially vertical and biased by their own weight against a multiplicity of orienting mechanisms. The orienting mechanisms are arranged to correspond to each wafer position within the cassette. The plurality of orienting mechanisms are intergrated with the supporting platform so that all wafers within the cassette can be aligned during this aligning process.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: August 7, 2001
    Assignee: Chartered Semiconductor Manufacturing Company
    Inventor: Vijai Sinha