Abstract: The disclosure provides data storage devices, methods, and apparatuses including, among other things, a NAND feature through which software may define logical die groups. Moreover, these logical die groups are indexed and operated with indexed single commands, which is selective-multi-casting to specific dies. In one implementation, a data storage device includes a NAND memory and a controller. The NAND memory including a plurality of dies. The controller is coupled to the NAND memory and configured to generate an index by assigning each die of the plurality of dies to one logical group of a plurality of logical groups, and create the plurality of logical groups in the NAND memory by sending one or more command sequences to the NAND memory that groups the plurality of dies into the plurality of logical groups based on the index that is generated.

Abstract: A memory circuit included in a computer system includes a memory array that stores multiple program instructions included in compressed program code. In response to receiving a fetch instruction from a processor circuit, the memory circuit may retrieve a particular instruction from the memory array. The memory circuit may, in response to a determination that the particular instruction is a particular type of instruction, retrieve additional program instructions from the memory array using an address included in the particular instruction, and send the particular program instruction and the additional program instructions to the processor circuit.

Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

Abstract: The disclosure provides data storage devices, methods, and apparatuses including, among other things, a NAND feature through which software may define logical die groups. Moreover, these logical die groups are indexed and operated with indexed single commands, which is selective-multi-casting to specific dies. In one implementation, a data storage device includes a NAND memory and a controller. The NAND memory including a plurality of dies. The controller is coupled to the NAND memory and configured to generate an index by assigning each die of the plurality of dies to one logical group of a plurality of logical groups, and create the plurality of logical groups in the NAND memory by sending one or more command sequences to the NAND memory that groups the plurality of dies into the plurality of logical groups based on the index that is generated.

Abstract: A data storage system includes a memory including a plurality of memory cells; and control logic configured to receive a first data string and determine a data type of the first data string. If the first data string is a combination command, the control logic obtains a plurality of sub-commands based on the first data string. Meanwhile, the control logic receives a second data string, determines that it represents an address, and decodes the address. While decoding the address or otherwise processing the second data string, the control logic performs a system operation specified by one of the sub-commands. The control logic also performs a memory operation, specified by another of the sub-commands, on one or more of the plurality of memory cells in accordance with the decoded address.

Abstract: Disclosed herein is a solid-state storage device that reduces read time for read time-sensitive data (“RTS data”). Data-characterizing logic characterizes incoming data from a host system as primary data including the RTS data or secondary data including non-RTS data. Memory-cell programming schemes include a primary data-programming scheme for a reduced read-frequency zone for the primary data and a secondary data-programming scheme standard read-frequency zone for the secondary data. Data routing logic routes the primary data to a plurality of physical pages corresponding to lower logical pages of a plurality of logical pages in the at-least-one reduced read-frequency zone with assistance by a logical-to-physical address translator. The lower logical pages require fewer read operations than upper logical pages of the plurality of logical pages to read the primary data, which results in a reduction of the read time for the RTS data in the at-least-one reduced read-frequency zone.

Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

Abstract: A data storage system includes a storage controller and a storage medium in communication with the storage controller. The storage medium includes a memory core comprising an array of memory cells and core control logic configured to perform operations on memory cells in the array in accordance with instructions received from the storage controller. The core control logic comprises a firmware-implemented condition evaluation machine configured to determine whether a plurality of memory core conditions are met. The core control logic also comprises a firmware-implemented signal setting machine configured to set or reset a plurality of respective memory operation signals to implement the operations on the memory cells based on respective condition evaluation machine determinations.

Abstract: A data storage system includes a memory including a plurality of memory cells; and control logic configured to receive a first data string and determine a data type of the first data string. If the first data string is a combination command, the control logic obtains a plurality of sub-commands based on the first data string. Meanwhile, the control logic receives a second data string, determines that it represents an address, and decodes the address. While decoding the address or otherwise processing the second data string, the control logic performs a system operation specified by one of the sub-commands. The control logic also performs a memory operation, specified by another of the sub-commands, on one or more of the plurality of memory cells in accordance with the decoded address.

Abstract: A memory circuit included in a computer system includes a memory array that stores multiple program instructions included in compressed program code. In response to receiving a fetch instruction from a processor circuit, the memory circuit may retrieve a particular instruction from the memory array. The memory circuit may, in response to a determination that the particular instruction is a particular type of instruction, retrieve additional program instructions from the memory array using an address included in the particular instruction, and send the particular program instruction and the additional program instructions to the processor circuit.

Abstract: A memory circuit included in a computer system stores multiple program instructions in program code. In response to fetching a loop boundary instruction, a processor circuit may store, in a loop storage circuit, a set of program instructions included in a program loop associated with the loop boundary instruction. In executing at least one iteration of the program loop, the processor circuit may retrieve the set of program instructions from the loop storage circuit.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.

Abstract: This disclosure provides techniques for debugging a computing system in a post-silicon validation process. In one example, a system can include a memory storing a set of instructions. The system can include a controller configured to fetch and execute the set of instructions. The system can include a logic block. The system can include a control bus coupling the memory, the controller, and the logic block. The control bus can include a first break-in circuit and a second break-in circuit each coupled to the controller. The first break-in circuit and the second break-in circuit can be configured to selectively cascade a break point from the controller through the logic block to halt execution of the set of instructions.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.