Patents by Inventor Vijay Janapaty

Vijay Janapaty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Efficient filtering of RxLOS signal in SerDes applications
    Patent number: 7260164
    Abstract: An efficient filter circuit and method for filtering a loss of receiver signal prevents false signals caused by glitches. The short glitches that happen at the positive edge of the clock signal may be prevented from affecting the whole clock cycle. The false signal removal circuitry is effective against both false active high and false active low signals. A selectable majority determination block also measures the number of glitches or average signal strength to determine that a valid signal is present. A mininum pulse width of a glitch is settable.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: August 21, 2007
    Assignee: LSI Corporation
    Inventors: Vijay Janapaty, Rishi Chugh, Rajinder Cheema
  • Efficient filtering of RxLOS signal in SerDes applications
    Publication number: 20040234015
    Abstract: An efficient filter circuit and method for filtering a loss of receiver signal prevents false signals caused by glitches. The short glitches that happen at the positive edge of the clock signal may be prevented from affecting the whole clock cycle. The false signal removal circuitry is effective against both false active high and false active low signals. A selectable majority determination block also measures the number of glitches or average signal strength to determine that a valid signal is present. A mininum pulse width of a glitch is settable.
    Type: Application
    Filed: May 23, 2003
    Publication date: November 25, 2004
    Inventors: Vijay Janapaty, Rishi Chugh, Rajinder Cheema