Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents is less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Abstract: Improved magnetic component models, circuit simulation systems and methods are presented for simulating operation of a modeled magnetic circuit component in which user input defines magnetically susceptible core geometry of the modeled magnetic circuit component, a core model simulates operation of the magnetically susceptible core at least partially according to the geometry of the magnetically susceptible core, and one or more coil models simulate operation of coils wound around the magnetically susceptible core to provide a scalable model with geometry adjustable permeability for fluxgate magnetic sensors, transformers, inductors or other modeled components.

Abstract: In some examples, an integrated circuit includes a plurality of power modules formed on a substrate, including a first power module located between second and third power modules. The first power module is configured to conduct a load current, and includes a power transistor and first and second sense transistors. The first sense transistor is disposed at a first position between the second power module and a central axis of the first power module, and the second sense transistor is disposed at a second position between the third power module and the central axis. The first sense transistor is configured to conduct a first sense current; and the second sense transistor is configured to conduct a second sense current. The first and second sense transistors are configured to direct the first and second sense currents toward a measurement circuit that is configured to determine a derived sense current indicative of the load current.

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents is less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Abstract: In some examples, an integrated circuit includes a plurality of power modules formed on a substrate, including a first power module located between second and third power modules. The first power module is configured to conduct a load current, and includes a power transistor and first and second sense transistors. The first sense transistor is disposed at a first position between the second power module and a central axis of the first power module, and the second sense transistor is disposed at a second position between the third power module and the central axis. The first sense transistor is configured to conduct a first sense current; and the second sense transistor is configured to conduct a second sense current. The first and second sense transistors are configured to direct the first and second sense currents toward a measurement circuit that is configured to determine a derived sense current indicative of the load current.

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Abstract: An electronic device comprises a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a first gate, a first terminal, and a second terminal; a first sense transistor integrated in the first semiconductor die, the first sense transistor comprising a second gate and third and fourth terminals, the second gate coupled to the first gate and the fourth terminal coupled to the second terminal; a first resistor integrated in the first semiconductor die, the first resistor has a first temperature coefficient; a second sense transistor integrated in the first semiconductor die, the second sense transistor comprising a third gate and seventh and eighth terminals, the third gate coupled to the first gate and the eighth terminal coupled to the second terminal; and a second resistor integrated in the first semiconductor die, the second resistor has a second temperature coefficient.

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Abstract: An electronic device comprises a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a first gate, a first terminal, and a second terminal; a first sense transistor integrated in the first semiconductor die, the first sense transistor comprising a second gate and third and fourth terminals, the second gate coupled to the first gate and the fourth terminal coupled to the second terminal; a first resistor integrated in the first semiconductor die, the first resistor has a first temperature coefficient; a second sense transistor integrated in the first semiconductor die, the second sense transistor comprising a third gate and seventh and eighth terminals, the third gate coupled to the first gate and the eighth terminal coupled to the second terminal; and a second resistor integrated in the first semiconductor die, the second resistor has a second temperature coefficient.

Abstract: An electronic device comprises: a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a gate, a first terminal, and a second terminal; a sense transistor integrated in the first semiconductor die, the sense transistor comprising a gate coupled to the gate of the power transistor, a first terminal, and a second terminal coupled to the second terminal of the power transistor; and a first resistor integrated in the first semiconductor die, the first resistor comprising a polysilicon section and a metal section coupled to the polysilicon section, the first resistor comprising a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first terminal of the sense transistor.

Abstract: An electronic device comprises: a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a gate, a first terminal, and a second terminal; a sense transistor integrated in the first semiconductor die, the sense transistor comprising a gate coupled to the gate of the power transistor, a first terminal, and a second terminal coupled to the second terminal of the power transistor; and a first resistor integrated in the first semiconductor die, the first resistor comprising a polysilicon section and a metal section coupled to the polysilicon section, the first resistor comprising a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first terminal of the sense transistor.

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Abstract: Improved magnetic component models, circuit simulation systems and methods are presented for simulating operation of a modeled magnetic circuit component in which user input defines magnetically susceptible core geometry of the modeled magnetic circuit component, a core model simulates operation of the magnetically susceptible core at least partially according to the geometry of the magnetically susceptible core, and one or more coil models simulate operation of coils wound around the magnetically susceptible core to provide a scalable model with geometry adjustable permeability for fluxgate magnetic sensors, transformers, inductors or other modeled components.