Patents by Inventor Vijay Krishnan

Vijay Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972627
    Abstract: A system and method for automating and improving data extraction from a variety of document types, including both unstructured, structured, and nested content, is disclosed. The system and method incorporate an intelligent machine learning model that is designed to intelligently identify chunks of text, map the fields in the document, and extract multi-record values. The system is designed to operate with little to no human intervention, while offering significant gains in accuracy, data visualization, and efficiency. The architecture applies customized techniques including density-based adaptive text clustering, tabular data extraction based on hierarchical intelligent keyword searches, and natural language processing-based field value selection.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: April 30, 2024
    Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Loganathan Muthu, Rahul Kotnala, Srinivasan Krishnan Rajagopalan, Peter Ashly Gopalan, Manikandan Chandran, Anand Yesuraj Prakash, Simantini Deb, Vijay Dhandapani, Harbhajan Singh, RBSanthosh Kumar, Lokesh Venkatappa, Ramakrishnan Raman
  • Publication number: 20230278075
    Abstract: Various embodiments of the present disclosure provide a multi-stage system and process for removing debris from plastic sheets (such as tier sheets or any other suitable sheets formed from any suitable material). Certain embodiments of the sheet-cleaning system (10) include a drive assembly comprising a drive roller (211, 212) driven by a drive actuator, an electrostatic-discharge device (220) operable to discharge static electricity, and a cleaning roller assembly (230) comprising a cleaning roller (231, 232) driven by a cleaning roller actuator, the cleaning roller (231, 232) comprising a cleaning implement on at least part of its outer surface.
    Type: Application
    Filed: August 17, 2021
    Publication date: September 7, 2023
    Inventors: Sanjoy Ghosh, Vijay Krishnan, Vishnuchitam Acharyulu Podicheti, Nizamuddin MD
  • Publication number: 20230120592
    Abstract: A query generation and processing system includes a relational data store, a query generator, and a query processor. The relational data store stores data ingested from data sources in a first and second datasets. The query generator interprets a data expression in a simplified query language to generate a query in a structured query language based on identifying quads corresponding to the first and second datasets in the data expression and determining an implicit join between the quads based on an unambiguous relationship obtainable from a schema of the first and datasets, in which the data expression does not expressly identify a join between the first quad and the second quad. The query processor generates a query pipeline that uses the data of the first and second datasets stored by the relational data store to execute the query generated by the query processor.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 20, 2023
    Inventors: Priyendra Singh Deshwal, Vijay Krishnan Ganesan, Abhishek Rai, Satyam Shekhar, Jordan Farr Hannel
  • Publication number: 20230118040
    Abstract: Data expressions in a simplified query language are processed to generate queries in a structured query language which can then be executed against data ingested from one or more data sources. The data expression is parsed to determine quads and to produce a tree of the quads. A derivation graph including nodes representing the quads and including at least one edge representing a derivation relationship between two of the quads determined based on attributes of the quads is generated based on the tree of quads and a data schema. The derivation graph is then queried based on a grain of the quads to generate the query. The simplified query language does not require an expression of a join relationship between the quads within the data expression when an unambiguous relationship between the quads is obtainable from the data schema.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 20, 2023
    Inventors: Priyendra Singh Deshwal, Jordan Farr Hannel, Vijay Krishnan Ganesan
  • Publication number: 20230119724
    Abstract: A derivation graph including nodes representing quads identified within a data expression in a simplified query language is queried using deferred join processing. A derivation graph is generated based on a first data expression that includes a join between a second data expression and a third data expression, in which the derivation graph includes at least one node representative of the second data expression and at least one node representative of the third data expression. A root node is identified within the derivation graph by determining that the nodes representative of the second data expression and the third data expression are derivable from the root node using the derivation graph. Query language instructions representing the join between the second data expression and the third data expression written in a second query language are then generated using the root node.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 20, 2023
    Applicant: NetSpring Data, Inc.
    Inventors: Priyendra Singh Deshwal, Jordan Farr Hannel, Vijay Krishnan Ganesan
  • Patent number: 11036615
    Abstract: A method of and system for performing pilot testing of a software program in an organization is carried out by collecting pilot testing data generated from a pilot testing of a software program run on one or more hardware assets in the organization, determining whether a sufficient amount of pilot testing data has been collected, and, when so, calculating one or more pilot test metrics from the collected data. The calculated pilot test metrics may then be compared to similar metrics in a target population to evaluate the software program.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 15, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vijay Krishnan, Sandipan Ganguly, Ritu Singh, Shashidhar Rajashekara, Muskan Kukreja
  • Patent number: 10977025
    Abstract: A system is disclosed, which includes a processor and a memory in communication with the processor. The memory includes executable instructions that, when executed by the processor, cause the processor to control the system to perform functions of collecting software asset information of software assets installed in hardware assets of an organization; determining popularity metrics of the software assets based on the collected software asset information; classifying, based on the popularity metrics, the software assets into a plurality of popularity groups; identifying, based on the classification, a pilot test software asset sample group; identifying, based on the pilot test software asset sample group, a pilot test hardware asset sample group; and deploying the new software asset to the pilot test hardware asset sample group for executing the pilot test of the new software asset.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: April 13, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vijay Krishnan, Muskan Kukreja, Sandi Ganguly
  • Patent number: 10929217
    Abstract: In one example, a system includes an electronic processor configured to receive telemetry data originating from a plurality of client applications. The telemetry data includes data points associated with errors associated with one or more operations. The electronic processor also classifies the telemetry data based a plurality of classes of data, converts the plurality of classes of data into one or more metrics based on a plurality of dimensions, and aggregates the metrics for the classes of data by all the dimensions. The electronic processor accesses a predictive scoring model for a stored metric associated with a dimension of interest, determines a prediction error associated with the dimension of interest, detects an anomaly based on an item selected from the group consisting of the prediction error and a static threshold, and transmits an alert message, generates a bug report, and stores the bug report in a database.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: February 23, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Muskan Kukreja, Fnu Vijay Krishnan, Uma Shankar V. Stanam, Michael C. Cales, Sandipan Ganguly
  • Publication number: 20200183811
    Abstract: A method of and system for performing pilot testing of a software program in an organization is carried out by collecting pilot testing data generated from a pilot testing of a software program run on one or more hardware assets in the organization, determining whether a sufficient amount of pilot testing data has been collected, and, when so, calculating one or more pilot test metrics from the collected data. The calculated pilot test metrics may then be compared to similar metrics in a target population to evaluate the software program.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 11, 2020
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Vijay KRISHNAN, Sandipan GANGULY, Ritu SINGH, Shashidhar RAJASHEKARA, Muskan KUKREJA
  • Publication number: 20200142685
    Abstract: A system is disclosed, which includes a processor and a memory in communication with the processor. The memory includes executable instructions that, when executed by the processor, cause the processor to control the system to perform functions of receiving software asset information of a plurality of software assets installed in a plurality of hardware assets of an organization; determining popularity metrics of the software assets based on the collected software asset information; classifying, based on the popularity metrics, the software assets into a plurality of popularity groups; identifying, based on the classification, a group of the software assets to be validated for a software update; identifying, based on the identified group of the software assets, a group of the hardware assets to be tested for the software update; and deploying the software update to the identified group of the hardware assets to validate the identified group of the software assets.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 7, 2020
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Vijay KRISHNAN, Muskan KUKREJA, Sandi GANGULY
  • Patent number: 10515914
    Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Mihir A. Oka, Ken P. Hackenberg, Vijay Krishnan (Vijay) Subramanian, Neha M. Patel, Nachiket R. Raravikar
  • Patent number: 10498630
    Abstract: A device including a processor and memory is disclosed. The memory includes executable instructions that cause the processor to control the device to perform functions of identifying a pool of assets to be covered by a pilot test; receiving attributes associated with the identified assets in the pool; identifying a set of pilot test parameters associated with the pilot test; comparing the attributes of the assets with the identified set of pilot test parameters associated with the pilot test; based on a result of the comparison, providing a unique ranked order of the identified assets in the pool and selecting an asset from the unique ranked order to be placed in a pilot test group. When a stop condition is not satisfied, a footprint of the asset placed in the pilot test group is removed from the pool and the set of pilot test parameters.
    Type: Grant
    Filed: July 14, 2018
    Date of Patent: December 3, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Shashidhar Rajashekara, Muskan Kukreja, Vijay Krishnan, Sandi Ganguly
  • Publication number: 20190294485
    Abstract: In one example, a system includes an electronic processor configured to receive telemetry data originating from a plurality of client applications. The telemetry data includes data points associated with errors associated with one or more operations. The electronic processor also classifies the telemetry data based a plurality of classes of data, converts the plurality of classes of data into one or more metrics based on a plurality of dimensions, and aggregates the metrics for the classes of data by all the dimensions. The electronic processor accesses a predictive scoring model for a stored metric associated with a dimension of interest, determines a prediction error associated with the dimension of interest, detects an anomaly based on an item selected from the group consisting of the prediction error and a static threshold, and transmits an alert message, generates a bug report, and stores the bug report in a database.
    Type: Application
    Filed: March 22, 2018
    Publication date: September 26, 2019
    Inventors: Muskan KUKREJA, FNU VIJAY KRISHNAN, Uma Shankar V. STANAM, Michael C. CALES, Sandipan GANGULY
  • Publication number: 20190157225
    Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.
    Type: Application
    Filed: January 29, 2019
    Publication date: May 23, 2019
    Inventors: Mihir A. OKA, Ken P. HACKENBERG, Vijay Krishnan (Vijay) SUBRAMANIAN, Neha M. PATEL, Nachiket R. RARAVIKAR
  • Patent number: 10224299
    Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Mihir A. Oka, Ken P. Hackenberg, Vijay Krishnan (Vijay) Subramanian, Neha M. Patel, Nachiket R. Raravikar
  • Publication number: 20180190604
    Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Mihir A. OKA, Ken P. HACKENBERG, Vijay Krishnan (Vijay) SUBRAMANIAN, Neha M. PATEL, Nachiket R. RARAVIKAR
  • Publication number: 20180144274
    Abstract: Generating an optimized supplier allocation plan includes identifying parts and suppliers associated with an allocation problem, where each supplier can supply at least one part. One or more objective functions are selected. Each objective function has part variables, and each part variable represents a quantity of a part to be procured from a supplier. At least one constraint constraining at least one part variable is received. The one or more objective functions are optimized with respect to the at least one constraint to yield a value for each part variable. A quantity of each part to be procured from at least one supplier is determined according to the values to generate the optimized supplier allocation plan.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 24, 2018
    Inventors: Vijay Krishnan Ganesan, Jian Yang, Gayle Lynne Hayes, Mark Richard Miller
  • Publication number: 20180089984
    Abstract: Techniques and mechanisms for determining a level of degradation of flexible circuitry. In an embodiment, a flexible substrate has disposed therein first circuitry and one or more components coupled thereto, the one or more components to monitor a physical property of the first circuitry. Further disposed in or on the flexible substrate are memory resources to store predefined reference information which corresponds amounts of the physical property each with a different respective level of degradation. Evaluation logic accesses the reference information to determine, based on a detected amount of the physical property, a level of degradation of second circuitry. In another embodiment, the second circuitry is more flexible, as compared to the first circuitry.
    Type: Application
    Filed: September 27, 2016
    Publication date: March 29, 2018
    Inventors: Vijay Krishnan Subramanian, Steven A. Klein, Pramod Malatkar, Rajendra C. Dias, Aleksandar Aleksov, Jason P. Glumbik, Nadine L. Dabby
  • Publication number: 20170287799
    Abstract: A stiffener, an IC package and methods of fabrication of an IC package including a removable stiffener are shown. A removable stiffener for use with an integrated circuit (IC), including a plurality of adhesive portions disposed between a surface of the stiffener and a surface of a substrate of the IC is shown. Such a removable stiffener including at least one removal tab is shown. An IC package including a removable stiffener including a plurality of adhesive portions disposed between a surface of the stiffener and a surface of a substrate of the IC is shown. Methods of fabrication of an IC package including a removable stiffener are shown.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: Steven A. Klein, Aditya S. Vaidya, Vijay Krishnan Subramanian, Santosh Sankarasubramanian, Pramod Malatkar, Suriyakala Suriya Ramalingam, Ashish Dhall
  • Publication number: 20170268972
    Abstract: Embodiments are generally directed to a lateral expansion apparatus for mechanical testing of stretchable electronics. An embodiment of a system includes a compressible cylinder to apply mechanical forces to a stretchable electronics device by the compression and release of the compressible cylinder; a compression unit to compress to the compressible cylinder, wherein the compression unit is to apply a compression force in a direction along an axis of the compressible cylinder to generate lateral expansion of the compressible cylinder; and a testing logic to control compression and release of the compressible cylinder.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: Vijay Krishnan SUBRAMANIAN, Steven A. KLEIN, Rajendra C. DIAS, Pramod MALATKAR, Aleksandar ALEKSOV, Ravindranath V. MAHAJAN, Robert L. SANKMAN