Patents by Inventor Vijay P. Kesan

Vijay P. Kesan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5525828
    Abstract: Silicon-VLSI-compatible photodetectors, in the form of a metal-semiconductor-metal photodetector (MSM-PD) or a lateral p-i-n photodetector (LPIN-PD), are disclosed embodying interdigitated metallic electrodes on a silicon surface. The electrodes of the MSM-PD have a moderate to high electron and hole barrier height to silicon, for forming the Schottky barriers, and are fabricated so as to be recessed in the surface semiconducting layer of silicon through the use of self-aligned metallization either by selective deposition or by selective reaction and etching, in a manner similar to the SALICIDE concept. Fabrication is begun by coating the exposed Si surface of a substrate with a transparent oxide film, such that the Si/oxide interface exhibits low surface recombination velocity.
    Type: Grant
    Filed: August 23, 1994
    Date of Patent: June 11, 1996
    Assignee: International Business Machines Corporation
    Inventors: Ernest Bassous, Jean-Marc Halbout, Subramanian S. Iyer, Rajiv V. Joshi, Vijay P. Kesan, Michael R. Scheuermann, Massimo A. Ghioni
  • Patent number: 5501787
    Abstract: A system for making porous silicon on blank and patterned Si substrates by "immersion scanning", particularly suitable for fabricating light-emitting Si devices and utilizing an open electrolytic cell having a cathode and an opposing anode consisting of a Si substrate on which the porous silicon is to be formed, both disposed, with their opposing surfaces in parallel, in an aqueous HF solution electrolyte contained in the cell. The substrate anode is mounted to be movable relative to the electrolyte so as to be mechanically cycled or scanned in and out of the electrolyte at a programmable rate during anodization. The uniformity, thickness and porosity of the resulting anodized layer on the substrate are determined by the scanning speed, number of cycles, current density, and HF-based electrolyte parameters of the system, and the Si substrate resistivity, conductivity type, and crystal orientation.
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: March 26, 1996
    Assignee: International Business Machines Corporation
    Inventors: Ernest Bassous, Jean-Marc Halbout, Subramanian S. Iyer, Vijay P. Kesan
  • Patent number: 5458756
    Abstract: A system for making porous silicon on blank and patterned Si substrates by "immersion scanning", particularly suitable for fabricating light-emitting Si devices and utilizing an open electolytic cell having a cathode and an opposing anode consisting of a Si substrate on which the porous silicon is to be formed, both disposed, with their opposing surfaces in parallel, in an aqueous HF solution electrolyte contained in the cell. The substrate anode is mounted to be movable relative to the electrolyte so as to be mechanically cycled or scanned in and out of the electrolyte at a programmable rate during anodization. The uniformity, thickness and porosity of the resulting anodized layer on the substrate are determined by the scanning speed, number of cycles, current density, and HF-based electrolyte parameters of the system, and the Si substrate resistivity, conductivity type, and crystal orientation.
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: October 17, 1995
    Assignee: International Business Machines Corporation
    Inventors: Ernest Bassous, Jean-Marc Halbout, Subramanian S. Iyer, Vijay P. Kesan
  • Patent number: 5268324
    Abstract: A process is disclosed for making CMOS devices with enhanced performance PMOS FETS by integrating germanium technology into a silicon-based fabrication method. Silicon-germanium layers are selectively grown on the surfaces of oxide-isolated PFET pockets of a silicon substrate previously prepared by a conventional silicon CMOS process. A silicon cap is deposited over each Si--Ge layer and gate insulator is formed over the cap provide gate dielectric for the PFETS. Gate insulator is formed over the NFET pockets to provide gate dielectric for the NFETS. Gate structures are completed along with source and drain junctions in accordance with normal practice. Provision also is made for the additional selective growth of a second silicon-germanium layer on the surfaces of oxide-isolated NFET pockets on the same CMOS substrate to enhance the performance of the NFETS as well as that of the PFETS.
    Type: Grant
    Filed: May 27, 1992
    Date of Patent: December 7, 1993
    Assignee: International Business Machines Corporation
    Inventors: John M. Aitken, Vijay P. Kesan, Seshadri Subbanna, Manu J. Tejwani, Subramanian S. Iyer
  • Patent number: 5034604
    Abstract: A device and method for producing an ultra pure molecular beam of elemental molecules utilizing a reduced thermal gradient filament construction in an effusion cell is provided. The effusion cell comprises a crucible having an open and a closed end and at least one heating filament distributed immediate the crucible. The at least one heating filament or filaments are provided having a first portion having a first pitch in proximal relationship to the open end of the crucible and having a second portion having a second pitch wherein the first pitch is of a higher spatial frequency than the second pitch. The heating filament is non-inductively wound about the crucible and positioned in conformity to the outside structure of the crucible. The heat shield is positioned proximate and about the crucible and heating filament or filaments. The heating filaments are connected to a controllable electric power supply producing a near constant temperature along the long axis of the crucible.
    Type: Grant
    Filed: August 29, 1989
    Date of Patent: July 23, 1991
    Assignee: Board of Regents, The University of Texas System
    Inventors: Ben G. Streetman, Terry J. Mattord, Vijay P. Kesan, Ben G. Treetman, Terry Mattord