Patents by Inventor Vijay Rajasekaran
Vijay Rajasekaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11671720Abstract: One example provides a method of generating a high dynamic range image via a differential TOF pixel comprising an array of pixels each having a first polyfinger and a second polyfinger, the first polyfinger and the second polyfinger being independently controllable to integrate current during an integration period, the method comprising, during the integration period, controlling the first polyfinger for a first exposure time, during the integration period, controlling the second polyfinger for a second exposure time, the second exposure time being shorter than the first exposure time, and for each pixel of the plurality of pixels, comparing a charge collected at the first polyfinger and a charge collected at the second polyfinger to a threshold, and selecting one of the charge collected at the first polyfinger and the charge collected at the second polyfinger for inclusion in the HDR image.Type: GrantFiled: August 8, 2019Date of Patent: June 6, 2023Assignee: Microsoft Technology Licensing, LLCInventor: Vijay Rajasekaran
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Publication number: 20210044767Abstract: One example provides a method of generating a high dynamic range image via a differential TOF pixel comprising an array of pixels each having a first polyfinger and a second polyfinger, the first polyfinger and the second polyfinger being independently controllable to integrate current during an integration period, the method comprising, during the integration period, controlling the first polyfinger for a first exposure time, during the integration period, controlling the second polyfinger for a second exposure time, the second exposure time being shorter than the first exposure time, and for each pixel of the plurality of pixels, comparing a charge collected at the first polyfinger and a charge collected at the second polyfinger to a threshold, and selecting one of the charge collected at the first polyfinger and the charge collected at the second polyfinger for inclusion in the HDR image.Type: ApplicationFiled: August 8, 2019Publication date: February 11, 2021Applicant: Microsoft Technology Licensing, LLCInventor: Vijay RAJASEKARAN
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Patent number: 10742912Abstract: Pixel arrangements in time-of-flight sensors are presented that include sensing elements that establish charges related to incident light, charge storage elements that accumulate integrated charges transferred from the sensing elements, and diffusion nodes configured to establish measurement voltages representative of the integrated charges that are dumped from the charge storage elements. The pixel arrangement includes analog domain output circuitry comprising a measurement capacitance element that stores the measurement voltage, and a reset capacitance element that stores a reset voltage established at the diffusion node during a reset phase performed prior to a measurement phase. The analog domain output circuitry subtracts the stored reset voltage from the stored measurement voltage for processing into a pixel output voltage that at least partially reduces readout voltage uncertainty of the pixel arrangement.Type: GrantFiled: July 5, 2019Date of Patent: August 11, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Cyrus Soli Bamji, Onur Can Akkaya, Tamer Elkhatib, Swati Mehta, Satyadev H. Nagaraja, Vijay Rajasekaran
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Publication number: 20190335124Abstract: Pixel arrangements in time-of-flight sensors are presented that include sensing elements that establish charges related to incident light, charge storage elements that accumulate integrated charges transferred from the sensing elements, and diffusion nodes configured to establish measurement voltages representative of the integrated charges that are dumped from the charge storage elements. The pixel arrangement includes analog domain output circuitry comprising a measurement capacitance element that stores the measurement voltage, and a reset capacitance element that stores a reset voltage established at the diffusion node during a reset phase performed prior to a measurement phase. The analog domain output circuitry subtracts the stored reset voltage from the stored measurement voltage for processing into a pixel output voltage that at least partially reduces readout voltage uncertainty of the pixel arrangement.Type: ApplicationFiled: July 5, 2019Publication date: October 31, 2019Inventors: Cyrus Soli Bamji, Onur Can Akkaya, Tamer Elkhatib, Swati Mehta, Satyadev H. Nagaraja, Vijay Rajasekaran
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Patent number: 10389957Abstract: Pixel arrangements in time-of-flight sensors are presented that include sensing elements that establish charges related to incident light, charge storage elements that accumulate integrated charges transferred from the sensing elements, and diffusion nodes configured to establish measurement voltages representative of the integrated charges that are dumped from the charge storage elements. The pixel arrangement includes analog domain output circuitry comprising a measurement capacitance element that stores the measurement voltage, and a reset capacitance element that stores a reset voltage established at the diffusion node during a reset phase performed prior to a measurement phase. The analog domain output circuitry subtracts the stored reset voltage from the stored measurement voltage for processing into a pixel output voltage that at least partially reduces readout voltage uncertainty of the pixel arrangement.Type: GrantFiled: December 20, 2016Date of Patent: August 20, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Cyrus Soli Bamji, Onur Can Akkaya, Tamer Elkhatib, Swati Mehta, Satyadev H. Nagaraja, Vijay Rajasekaran
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Publication number: 20180176492Abstract: Pixel arrangements in time-of-flight sensors are presented that include sensing elements that establish charges related to incident light, charge storage elements that accumulate integrated charges transferred from the sensing elements, and diffusion nodes configured to establish measurement voltages representative of the integrated charges that are dumped from the charge storage elements. The pixel arrangement includes analog domain output circuitry comprising a measurement capacitance element that stores the measurement voltage, and a reset capacitance element that stores a reset voltage established at the diffusion node during a reset phase performed prior to a measurement phase. The analog domain output circuitry subtracts the stored reset voltage from the stored measurement voltage for processing into a pixel output voltage that at least partially reduces readout voltage uncertainty of the pixel arrangement.Type: ApplicationFiled: December 20, 2016Publication date: June 21, 2018Inventors: Cyrus Soli Bamji, Onur Can Akkaya, Tamer Elkhatib, Swati Mehta, Satyadev H. Nagaraja, Vijay Rajasekaran
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Patent number: 8724002Abstract: An imaging system may include imaging pixels. Each imaging pixel may include a reset transistor and a dummy transistor coupled to a floating diffusion storage node. When reset signals control are deasserted, capacitive coupling between the gate terminal of the reset transistor and the source-drain terminals of the reset transistor may lead to reset charge injection. The dummy transistor may have both of its source-drain terminals shorted together and shorted to the floating diffusion region. Dummy control signals, which may be provided by separate dummy control lines or may be provided using row-select signals, may be asserted on the dummy transistors at approximately the same time that the reset signals are deasserted. With arrangements of this type, the dummy control signals may inject an approximately equal and opposite charge onto the floating diffusion region, thereby reducing the reset charge injection caused by deasserting the reset control signals.Type: GrantFiled: March 1, 2011Date of Patent: May 13, 2014Assignee: Aptina Imaging CorporationInventor: Vijay Rajasekaran
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Publication number: 20120218451Abstract: An imaging system may include imaging pixels. Each imaging pixel may include a reset transistor and a dummy transistor coupled to a floating diffusion storage node. When reset signals control are deasserted, capacitive coupling between the gate terminal of the reset transistor and the source-drain terminals of the reset transistor may lead to reset charge injection. The dummy transistor may have both of its source-drain terminals shorted together and shorted to the floating diffusion region. Dummy control signals, which may be provided by separate dummy control lines or may be provided using row-select signals, may be asserted on the dummy transistors at approximately the same time that the reset signals are deasserted. With arrangements of this type, the dummy control signals may inject an approximately equal and opposite charge onto the floating diffusion region, thereby reducing the reset charge injection caused by deasserting the reset control signals.Type: ApplicationFiled: March 1, 2011Publication date: August 30, 2012Inventor: Vijay Rajasekaran
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Publication number: 20090272881Abstract: A method, apparatus, and system providing a pixel having increased fill factor by removing the row select transistor. A reset transistor in the pixel is connected to a column line, and the column line is used alternatively as a pixel readout line and as a voltage supply line for resetting a storage region in the pixel through the resent transistor.Type: ApplicationFiled: May 5, 2008Publication date: November 5, 2009Inventors: Xiangli Li, Vijay Rajasekaran