Abstract: A power amplifier (PA) provides dynamic stability and gain control for linear and non-linear operation. The PA operates with a baseband processor and a transmitter, in which the PA receives a signal from the transmitter for power amplification prior to transmission of the signal. The PA is configured to select between the linear mode of operation and the non-linear mode of operation, in which device scaling within the PA is achieved by changing a device sizing of at least one stage of the PA. Further to changing the device size, the PA changes biasing resistance and impedance of a matching network in response to the changing of the device size to control power output and stability for the PA.

Abstract: Bias circuitry that may be used within a communications or other device includes a first current mirror having first and second transistors with sources coupled to ground and operable to receive a reference current at a drain of first transistor. A second current mirror has first and second transistors with drains coupled to a battery voltage supply. A third current mirror has first and second transistors with drains coupled to sources of the first and second transistors of the second current mirror, respectively. A biasing transistor couples between the second transistor of the first current mirror and the first transistor of the third current mirror and operable to receive a tuning input voltage at its gate. A resistive element coupled between the second transistor of the third current mirror and ground produces a bias voltage produced at a connection of the resistive element and the second transistor of the third current mirror.

Abstract: A power amplifier (PA) provides dynamic stability and gain control for linear and non-linear operation. The PA operates with a baseband processor and a transmitter, in which the PA receives a signal from the transmitter for power amplification prior to transmission of the signal. The PA is configured to select between the linear mode of operation and the non-linear mode of operation, in which device scaling within the PA is achieved by changing a device sizing of at least one stage of the PA. Further to changing the device size, the PA changes biasing resistance and impedance of a matching network in response to the changing of the device size to control power output and stability for the PA.

Abstract: Bias circuitry that may be used within a communications or other device includes a first current mirror having first and second transistors with sources coupled to ground and operable to receive a reference current at a drain of first transistor. A second current mirror has first and second transistors with drains coupled to a battery voltage supply. A third current mirror has first and second transistors with drains coupled to sources of the first and second transistors of the second current mirror, respectively. A biasing transistor couples between the second transistor of the first current mirror and the first transistor of the third current mirror and operable to receive a tuning input voltage at its gate. A resistive element coupled between the second transistor of the third current mirror and ground produces a bias voltage produced at a connection of the resistive element and the second transistor of the third current mirror.