Patents by Inventor Vijayavardhan BAIREDDY
Vijayavardhan BAIREDDY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220408106Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: ApplicationFiled: August 23, 2022Publication date: December 22, 2022Inventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry
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Patent number: 11445207Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: GrantFiled: December 16, 2019Date of Patent: September 13, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry
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Publication number: 20220156322Abstract: Graph reordering and tiling techniques are described herein. In one example, large graphs (e.g., for inferencing with graph neural networks) can be reordered, tiled, or both, to achieve maximal data reuse and uniform compute load distribution. In one example, a reordering method involves performing breadth first search (BFS) renumbering on a graph data set with the highest degree destination node as the root node to generate a reordered graph data set. BFS is then performed again with candidate nodes from the last level of the reordered graph. The second reordered graph data set with the lowest bandwidth or best profile can be selected for further processing. In one example, a method of tiling involves dividing a graph data set into tiles to balance expected compute time.Type: ApplicationFiled: November 23, 2021Publication date: May 19, 2022Inventors: Tarjinder SINGH, Sridhar SR, Ranga SUMIRAN, Bakshree MISHRA, Srajudheen MAKKADAYIL, Vidhya THYAGARAJAN, Vijayavardhan BAIREDDY
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Publication number: 20200120351Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry
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Patent number: 10547859Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: GrantFiled: July 19, 2017Date of Patent: January 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry
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Patent number: 10536258Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.Type: GrantFiled: June 2, 2018Date of Patent: January 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hunsoo Choo, Hamid Safiri, Nikolaus Klemmer, Jaimin Mehta, Srinadh Madhavapeddi, Charles Kasimer Sestok, Vijayavardhan Baireddy
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Publication number: 20190372747Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.Type: ApplicationFiled: June 2, 2018Publication date: December 5, 2019Inventors: Hunsoo Choo, Hamid Safiri, Nikolaus Klemmer, Jaimin Mehta, Srinadh Madhavapeddi, Charles Kasimer Sestok, Vijayavardhan Baireddy
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Publication number: 20170318304Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Inventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry
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Publication number: 20150271512Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.Type: ApplicationFiled: March 18, 2015Publication date: September 24, 2015Inventors: Hetul Sanghvi, Mihir Narendra Mody, Niraj Nandan, Mahesh Madhukar Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Venkata Shastry
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Publication number: 20080071848Abstract: A butterfly processor architecture including a single high speed multiplier unit and two adder/subtracter units structured to efficiently perform radix-2 decimation-in-time (DIT) butterfly operations is disclosed. The computations for windowing operations, FFT operations, and IFFT operations may be realized in terms of butterfly operations. Therefore, the butterfly processor architecture may be used to perform the computations of a plurality of signal processing operations. The butterfly operations may be performed in-place whereby the results of each operation may be stored in the same location in memory where the inputs for each operation were retrieved. Performing the butterfly operations in-place ensures that the memory may be big enough to hold one frame of data.Type: ApplicationFiled: September 4, 2007Publication date: March 20, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Vijayavardhan BAIREDDY, Himamshu Gopalakrishna KHASNIS, Rajesh Hargovind MUNDHADA, Georgios GINIS