Patents by Inventor Vikas R. Sheth

Vikas R. Sheth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140061910
    Abstract: A method of making a semiconductor device can comprise forming a copper bond pad on an integrated circuit device; forming a first passivation layer on the integrated circuit device and the copper bond pad; forming a second passivation layer on the first passivation layer; forming a mask over the first and second passivation layers around the copper bond pad; etching the second passivation layer over the copper bond pad; and cleaning the first passivation layer over the copper bond pad. At least a portion of the first passivation layer remains over the copper bond pad after the etching the second passivation layer. A thickness of the first passivation layer over the copper bond pad is selected to protect the copper bond pad from oxidation and to allow wire bonding to the copper bond pad through the first passivation layer.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Inventors: CHU-CHUNG LEE, VIKAS R. SHETH
  • Patent number: 7670760
    Abstract: A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: March 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinmiao James Shen, Jonathan L. Cobb, William D. Darlington, Brian J. Fisher, Mark D. Hall, Vikas R. Sheth, Mehul D. Shroff, James E. Vasek
  • Patent number: 7176130
    Abstract: A method for forming a semiconductor device (10) includes forming an organic anti-reflective coating (OARC) layer (18) over the semiconductor device (10). A tetra-ethyl-ortho-silicate (TEOS) layer (20) is formed over the OARC layer (18). The TEOS layer (20) is exposed to oxygen-based plasma at a temperature of at most about 300 degrees Celsius. In an alternative embodiment, the TEOS layer (20) is first exposed to a nitrogen-based plasma before being exposed to the oxygen-based plasma. A photoresist layer (22) is formed over the TEOS layer (20) and patterned. By applying oxygen based plasma and nitrogen based plasma to the TEOS layer (20) before applying photoresist, pattern defects are reduced.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: February 13, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jin Miao Shen, Brian J. Fisher, Mark D. Hall, Kurt H. Junker, Vikas R. Sheth, Mehul D. Shroff