Patents by Inventor Vikash Banthia
Vikash Banthia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220344134Abstract: Methods and apparatus for processing substrates are provided herein. In some embodiments, a process kit for a substrate support includes: an upper edge ring made of quartz and having an upper surface and a lower surface, wherein the upper surface is substantially planar and the lower surface includes a stepped lower surface to define a radially outermost portion and a radially innermost portion of the upper edge ring.Type: ApplicationFiled: July 11, 2022Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventors: Muhannad MUSTAFA, Muhammad M. RASHEED, Yu LEI, Avgerinos V. GELATOS, Vikash BANTHIA, Victor H. CALDERON, Shi Wei TOH, Yung-Hsin LEE, Anindita SEN
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Patent number: 11421322Abstract: Embodiments of a blocker plate for use in a substrate process chamber are disclosed herein. In some embodiments, a blocker plate for use in a substrate processing chamber configured to process substrates having a given diameter includes: an annular rim; a central plate disposed within the annular rim; and a plurality of spokes coupling the central plate to the annular rim.Type: GrantFiled: July 24, 2019Date of Patent: August 23, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Xiaoxiong Yuan, Yu Lei, Yi Xu, Kazuya Daito, Pingyan Lei, Dien-Yeh Wu, Umesh M. Kelkar, Vikash Banthia
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Patent number: 11387134Abstract: Methods and apparatus for processing substrates are provided herein. In some embodiments, a process kit for a substrate support includes: an upper edge ring made of quartz and having an upper surface and a lower surface, wherein the upper surface is substantially planar and the lower surface includes a stepped lower surface to define a radially outermost portion and a radially innermost portion of the upper edge ring.Type: GrantFiled: January 16, 2019Date of Patent: July 12, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Muhannad Mustafa, Muhammad M. Rasheed, Yu Lei, Avgerinos V. Gelatos, Vikash Banthia, Victor H. Calderon, Shi Wei Toh, Yung-Hsin Lee, Anindita Sen
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Patent number: 11355391Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.Type: GrantFiled: February 27, 2020Date of Patent: June 7, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Xi Cen, Feiyue Ma, Kai Wu, Yu Lei, Kazuya Daito, Yi Xu, Vikash Banthia, Mei Chang, He Ren, Raymond Hoiman Hung, Yakuan Yao, Avgerinos V. Gelatos, David T. Or, Jing Zhou, Guoqiang Jian, Chi-Chou Lin, Yiming Lai, Jia Ye, Jenn-Yue Wang
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Patent number: 11249386Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate having a first side and a second side; a backside coating layer comprising an alloy of tantalum and nickel on the first side of the substrate; a multilayer stack of reflective layers on the second side of the substrate, the multilayer stack of reflective layers including a plurality of reflective layers including reflective layer pairs; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer.Type: GrantFiled: October 24, 2019Date of Patent: February 15, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Vibhu Jindal, Madhavi R Chandrachood, Vikash Banthia
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Patent number: 10879081Abstract: Methods and apparatus for reducing and eliminating defects in tungsten film are disclosed herein. In the present disclosure, reducing or eliminating oxidation of a first surface of a tungsten film having a predetermined first thickness disposed upon a substrate and within a plurality of trenches is disclosed. The plurality of trenches include a predetermined depth, and a width of less than 20 nanometers. The predetermined first thickness of the tungsten film is substantially uniform throughout the plurality of trenches such that the predetermined first thickness of the tungsten film does not substantially change to a second thickness when the first surface is contacted with air or oxygen.Type: GrantFiled: November 20, 2018Date of Patent: December 29, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Guoqiang Jian, Wei Tang, Chi-Chou Lin, Paul F. Ma, Kai Wu, Vikash Banthia, Mei Chang, Jia Ye, Wenyu Zhang, Jing Zhou
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Publication number: 20200303250Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.Type: ApplicationFiled: February 27, 2020Publication date: September 24, 2020Inventors: Xi CEN, Feiyue MA, Kai WU, Yu LEI, Kazuya DAITO, Yi XU, Vikash BANTHIA, Mei CHANG, He REN, Raymond Hoiman HUNG, Yakuan YAO, Avgerinos V. GELATOS, David T. OR, Jing ZHOU, Guoqiang JIAN, Chi-Chou LIN, Yiming LAI, Jia YE, Jenn-Yue WANG
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Patent number: 10727119Abstract: Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.Type: GrantFiled: January 18, 2019Date of Patent: July 28, 2020Assignee: Applied Materials, Inc.Inventors: He Ren, Feiyue Ma, Yu Lei, Kai Wu, Mehul B. Naik, Zhiyuan Wu, Vikash Banthia, Hua Ai
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Patent number: 10704147Abstract: Embodiments of the present disclosure are directed process kits for use with an in-chamber heater and substrate rotating mechanism. In some embodiments consistent with the present disclosure, a process kit for use with a rotatable substrate support heater pedestal for supporting a substrate in a process chamber may include an upper edge ring including a top ledge and a skirt the extends downward from the top ledge, a lower edge ring that at least partially supports the upper edge ring and aligns the upper edge ring with the substrate support heater pedestal, a bottom plate disposed on a bottom of the process chamber that supports the upper edge ring when the substrate support heater pedestal is in a lowered non-processing position, and a shadow ring that couples with the upper edge ring when the substrate support heater pedestal is in a raised processing position.Type: GrantFiled: February 1, 2017Date of Patent: July 7, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Muhammad M. Rasheed, Muhannad Mustafa, Hamid Tavassoli, Steven V Sansoni, Cheng-Hsiung Tsai, Vikash Banthia
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Publication number: 20200133114Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate having a first side and a second side; a backside coating layer comprising an alloy of tantalum and nickel on the first side of the substrate; a multilayer stack of reflective layers on the second side of the substrate, the multilayer stack of reflective layers including a plurality of reflective layers including reflective layer pairs; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer.Type: ApplicationFiled: October 24, 2019Publication date: April 30, 2020Inventors: Vibhu Jindal, Madhavi R. Chandrachood, Vikash Banthia
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Patent number: 10535527Abstract: A method for forming a film on a substrate in a semiconductor process chamber includes forming a first layer on the substrate using a plasma enhanced process and a gas compound of a chloride-based gas, a hydrogen gas, and an inert gas. The process chamber is then purged and the first layer is thermally soaked with a hydrogen-based precursor gas. The process chamber is then purged again and the process may be repeated with or without the plasma enhanced process until a certain film thickness is achieved on the substrate.Type: GrantFiled: July 6, 2018Date of Patent: January 14, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Yi Xu, Takashi Kuratomi, Avgerinos V. Gelatos, Vikash Banthia, Mei Chang, Kazuya Daito
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Publication number: 20190382895Abstract: Embodiments of a blocker plate for use in a substrate process chamber are disclosed herein. In some embodiments, a blocker plate for use in a substrate processing chamber configured to process substrates having a given diameter includes: an annular rim; a central plate disposed within the annular rim; and a plurality of spokes coupling the central plate to the annular rim.Type: ApplicationFiled: July 24, 2019Publication date: December 19, 2019Inventors: XIAOXIONG YUAN, YU LEI, YI XU, KAZUYA DAITO, PINGYAN LEI, DIEN-YEH WU, UMESH M. KELKAR, VIKASH BANTHIA
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Publication number: 20190385838Abstract: Methods to selectively deposit a film on a first surface (e.g., a metal surface) relative to a second surface (e.g., a dielectric surface) by exposing the surface to a pre-clean plasma comprising one or more of argon or hydrogen followed by deposition. The first surface and the second surface can be substantially coplanar. The selectivity of the deposited film may be increased by an order of magnitude relative to the substrate before exposure to the pre-cleaning plasma.Type: ApplicationFiled: August 26, 2019Publication date: December 19, 2019Inventors: Kai Wu, Vikash Banthia, Sang Ho Yu, Mei Chang, Feiyue Ma
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Patent number: 10508339Abstract: Embodiments of a blocker plate for use in a substrate process chamber are disclosed herein. In some embodiments, a blocker plate for use in a substrate processing chamber configured to process substrates having a given diameter includes: an annular rim; a central plate disposed within the annular rim; and a plurality of spokes coupling the central plate to the annular rim.Type: GrantFiled: July 29, 2017Date of Patent: December 17, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Xiaoxiong Yuan, Yu Lei, Yi Xu, Kazuya Daito, Pingyan Lei, Dien-Yeh Wu, Umesh M. Kelkar, Vikash Banthia
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Patent number: 10395916Abstract: Methods to selectively deposit a film on a first surface (e.g., a metal surface) relative to a second surface (e.g., a dielectric surface) by exposing the surface to a pre-clean plasma comprising one or more of argon or hydrogen followed by deposition. The first surface and the second surface can be substantially coplanar. The selectivity of the deposited film may be increased by an order of magnitude relative to the substrate before exposure to the pre-cleaning plasma.Type: GrantFiled: September 8, 2017Date of Patent: August 27, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Kai Wu, Vikash Banthia, Sang Ho Yu, Mei Chang, Feiyue Ma
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Publication number: 20190229007Abstract: Methods and apparatus for processing substrates are provided herein. In some embodiments, a process kit for a substrate support includes: an upper edge ring made of quartz and having an upper surface and a lower surface, wherein the upper surface is substantially planar and the lower surface includes a stepped lower surface to define a radially outermost portion and a radially innermost portion of the upper edge ring.Type: ApplicationFiled: January 16, 2019Publication date: July 25, 2019Inventors: MUHANNAD MUSTAFA, MUHAMMAD M. RASHEED, YU LEI, AVGERINOS V. GELATOS, VIKASH BANTHIA, VICTOR H. CALDERON, SHI WEI TOH, YUNG-HSIN LEE, ANINDITA SEN
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Publication number: 20190157145Abstract: Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.Type: ApplicationFiled: January 18, 2019Publication date: May 23, 2019Inventors: He REN, Feiyue MA, Yu LEI, Kai WU, Mehul B. NAIK, Zhiyuan WU, Vikash BANTHIA, Hua AI
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Publication number: 20190157102Abstract: Methods and apparatus for reducing and eliminating defects in tungsten film are disclosed herein. In the present disclosure, reducing or eliminating oxidation of a first surface of a tungsten film having a predetermined first thickness disposed upon a substrate and within a plurality of trenches is disclosed. The plurality of trenches include a predetermined depth, and a width of less than 20 nanometers. The predetermined first thickness of the tungsten film is substantially uniform throughout the plurality of trenches such that the predetermined first thickness of the tungsten film does not substantially change to a second thickness when the first surface is contacted with air or oxygen.Type: ApplicationFiled: November 20, 2018Publication date: May 23, 2019Inventors: GUOQIANG JIAN, WEI TANG, CHI-CHOU LIN, PAUL F. MA, KAI WU, VIKASH BANTHIA, MEI CHANG, JIA YE, WENYU ZHANG, JING ZHOU
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Patent number: 10256076Abstract: Methods of etching include cycles of low temperature etching of a material layer disposed on a substrate, with at least one of the cycles being followed by activation of unreacted etchant deposits during an inert gas plasma treatment. In some embodiments, a method includes: positioning a substrate in a processing chamber; generating, in a first etching cycle, a plasma from a gas mixture within the processing chamber to form a processing gas including an etchant; exposing, to the etchant, a portion of a material layer disposed on a substrate maintained at a first temperature; generating an inert gas plasma within the processing chamber; generating, in a second etching cycle, a plasma from a gas mixture within the processing chamber to form a processing gas including an etchant; and heating the substrate to a second temperature to sublimate a byproduct of reaction between the etchant and the material layer.Type: GrantFiled: December 30, 2015Date of Patent: April 9, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Shi Wei Toh, Avgerinos V. Gelatos, Vikash Banthia
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Patent number: 10256144Abstract: Embodiments of the present disclosure generally relate an interconnect formed on a substrate and a method of forming the interconnect thereon. In an embodiment, a via and trench in a stack formed on the substrate. A bottom of the via is pre-treated using a first pre-treatment procedure. A sidewall of the via is pre-treated using a second pre-treatment procedure. A first metal fill material of a first type is deposited on the stack, in the via. A second metal fill material of a second type is deposited on the stack, in the trench.Type: GrantFiled: April 26, 2017Date of Patent: April 9, 2019Assignee: Applied Materials, Inc.Inventors: He Ren, Feiyue Ma, Yu Lei, Kai Wu, Mehul B. Naik, Zhiyuan Wu, Vikash Banthia, Hua Al