Abstract: In some examples, a circuit includes a state machine. The state machine is configured to operate in a first state in which the state machine gates a pulse width modulation (PWM) signal provided for control of a power converter according to a first signal provided by a voltage control loop. The state machine is configured to operate in a second state in which the state machine gates the PWM signal according to a second signal provided by a current limit comparator. The state machine is configured to transition from the first state to the second state responsive to the second signal being asserted after the first signal is asserted in a switching cycle of the power converter. The state machine is configured to transition from the current state to the first state responsive to the first signal being asserted after the second signal in a switching cycle of the power converter.

Abstract: In some examples, a circuit includes a state machine. The state machine is configured to operate in a first state in which the state machine gates a pulse width modulation (PWM) signal provided for control of a power converter according to a first signal provided by a voltage control loop. The state machine is configured to operate in a second state in which the state machine gates the PWM signal according to a second signal provided by a current limit comparator. The state machine is configured to transition from the first state to the second state responsive to the second signal being asserted after the first signal is asserted in a switching cycle of the power converter. The state machine is configured to transition from the current state to the first state responsive to the first signal being asserted after the second signal in a switching cycle of the power converter.

Abstract: In some examples, a circuit includes a state machine. The state machine is configured to operate in a first state in which the state machine gates a pulse width modulation (PWM) signal provided for control of a power converter according to a first signal provided by a voltage control loop. The state machine is configured to operate in a second state in which the state machine gates the PWM signal according to a second signal provided by a current limit comparator. The state machine is configured to transition from the first state to the second state responsive to the second signal being asserted after the first signal is asserted in a switching cycle of the power converter. The state machine is configured to transition from the current state to the first state responsive to the first signal being asserted after the second signal in a switching cycle of the power converter.

Abstract: In at least some examples, an integrated circuit includes an input pin and an analog-to-digital converter (ADC) comprising an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit. In an example, the resistance circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.

Abstract: In at least some examples, an integrated circuit includes an input pin and an analog-to-digital converter (ADC) comprising an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit. In an example, the resistance circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.

Abstract: The disclosure provides a multi-phase converter. The multi-phase converter includes a controller and one or more switches. The one or more switches are coupled to the controller, and configured to receive an input voltage. A switch of the one or more switches is activated by the controller in a predefined phase of N phases in the multi-phase converter, where N is a positive integer. A processing unit is coupled to the controller and estimates a number of phases to be activated based on a load current. The processing unit also stores a threshold current limit corresponding to each phase of the N phases based on the input voltage and a switching frequency.

Abstract: A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Abstract: A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Abstract: A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Abstract: A control circuit for a DC-DC converter and a DC-DC converter are disclosed. The control circuit includes an integrator coupled to receive a first reference voltage and a first voltage that includes an output voltage for the DC-DC converter and to provide an integrated error signal. A first comparator is coupled to receive the first reference voltage and the first voltage and to provide a dynamic-integration signal that adjusts the integration time constant of the integrator.

Abstract: In a described example, a method includes using a power supply, supplying an output voltage that varies in response to a reference voltage; detecting a voltage ramp in an input reference voltage; generating an offset voltage waveform; adding the offset voltage waveform to the input reference voltage to generate a second reference voltage; and using the second reference voltage, operating the power supply to supply the output voltage.

Abstract: A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Abstract: A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Abstract: A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.

Abstract: A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Abstract: A control circuit for a DC-DC converter and a DC-DC converter are disclosed. The control circuit includes an integrator coupled to receive a first reference voltage and a first voltage that includes an output voltage for the DC-DC converter and to provide an integrated error signal. A first comparator is coupled to receive the first reference voltage and the first voltage and to provide a dynamic-integration signal that adjusts the integration time constant of the integrator.

Abstract: A voltage converter includes a high side power transistor coupled to an input voltage node and a low side power transistor coupled to the high side power transistor at a switch node. The switch node is configured to be coupled to an inductor. A slope detector circuit is configured to receive a signal indicative of a current through the inductor. The inductor current is a triangular waveform comprising a ramp-up phase and a ramp-down phase. The slope detector circuit also is configured to generate an output signal encoding when the inductor current is ramping up and when the inductor current is ramping down.

Abstract: In a described example, a method includes using a power supply, supplying an output voltage that varies in response to a reference voltage; detecting a voltage ramp in an input reference voltage; generating an offset voltage waveform; adding the offset voltage waveform to the input reference voltage to generate a second reference voltage; and using the second reference voltage, operating the power supply to supply the output voltage.

Abstract: A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.

Abstract: A voltage regulator includes a measurement circuit for obtaining a value representing a magnitude of an output capacitance connected at an output node of the voltage regulator. A correction circuit in the voltage regulator modifies a compensation circuit internal to the voltage regulator based on the value. The modification of the compensation circuit is done to ensure that sufficient stability margins to accommodate the output capacitance are ensured for the main feedback loop in the voltage regulator. In an embodiment, a voltage proportional to the output capacitance is detected at start-up of the voltage regulator, and a corresponding binary signal is generated. The logic value of the binary signal is used to add or remove components and/or circuit portions in the compensation circuit to ensure stability. The voltage regulator is thus designed to support a wide range of output capacitance values.