Abstract: A matrix multiplication and addition (MAC) operating system is described where different cell currents flowing through different cells in a matrix for different PWM time intervals can be integrated and converted into a numeric value for the cumulative charge. The numeric value of the cumulative charge computed by the ADC is equivalent to MAC operations over multiplicity of cells. The operation is inherently error prone due to parasitic coupling effects from the switching of the memory cells in the array. The presented system minimizes the errors due to parasitic coupling through memory array.

Abstract: In one aspect, an analog to digital converter (ADC) for a multiply-accumulator (MAC) system comprising: an ADC control that receives a VREF and generates a plurality of timing signals to an ADC, and wherein the plurality of timing signals comprises an S1 signal, an S3 signal, an S4 signal, an ECO signal, a CLOCK signal, and a COUNTER<N:0> signal; the ADC that comprises: a pre-charge system comprising a sense capacitor that stores an integrated charge IMAC over a time T and develops voltage VMAC, and wherein the S1 signal defines the pre-charge phase of the sense capacitor.

Abstract: In one aspect, a method for NOR flash cell-array programming in a neural circuit includes the step of erasing a cell array. The method includes the step of programming a set of reference cells of a reference cell array to a target reference threshold voltage (Vt_ref). The method includes the step of generating, with the reference cells, a current or voltage, reference signal. The method includes the step of using the reference signal to bias the neural cells during verification of program state of the neural cells to achieve their respective target threshold voltages (Vt_cell). The method includes the step of programming a set of neural cells of a neural cell array to their respective target threshold voltages.

Abstract: The method provides for a low power and a temperature independent analog to digital convertor for systems which use non-volatile cells for forming neurons to be used for neural network applications. The method uses a common counter which can be an up-counter or a down-counter depending on implementation, but in which the source and sink currents to a comparator are changed with temperature by the same percentage as the average bit line current for specific weight distributions programmed in the non-volatile cells forming the neurons. The method uses charge accumulation for detecting the average neuron current.

Abstract: In one aspect, a system for analog in-memory compute for a neural network includes an array of neurons. Each neuron of the array of neurons receives a pulse of magnitude xi, and duration t, wherein a product xi*yi provides a current proportional to the input for a time duration t, which is a charge associated with a particular neuron in response to the input being presented to that particular neuron. A reference cell includes a gate-drain connected flash cell configuration and coupled with the array of neurons. The reference cell is programmed to a pre-determined threshold voltage Vt-ref. The reference cell receives a pre-determined current, Iref, wherein, based on the Iref and a pre-determined threshold voltage Vt-ref, a voltage is created at a drain of the reference cell.

Abstract: In one aspect, a system for analog in-memory compute for a neural network includes an array of neurons. Each neuron of the array of neurons receives a pulse of magnitude xi, and duration t, wherein a product xi*yi provides a current proportional to the input for a time duration t, which is a charge associated with a particular neuron in response to the input being presented to that particular neuron. A reference cell includes a gate-drain connected flash cell configuration and coupled with the array of neurons. The reference cell is programmed to a pre-determined threshold voltage Vt-ref.

Abstract: The method provides for a low power and a temperature independent analog to digital convertor for systems which use non-volatile cells for forming neurons to be used for neural network applications. The method uses a common counter which can be an up-counter or a down-counter depending on implementation, but in which the source and sink currents to a comparator are changed with temperature by the same percentage as the average bit line current for specific weight distributions programmed in the non-volatile cells forming the neurons. The method uses charge accumulation for detecting the average neuron current.

Abstract: In one aspect, a method for NOR flash cell-array programming in a neural circuit includes the step of erasing a cell array. The method includes the step of programming a set of reference cells of a reference cell array to a target reference threshold voltage (Vt_ref). The method includes the step of generating, with the reference cells, a current or voltage, reference signal. The method includes the step of using the reference signal to bias the neural cells during verification of program state of the neural cells to achieve their respective target threshold voltages (Vt_cell). The method includes the step of programming a set of neural cells of a neural cell array to their respective target threshold voltages.

Abstract: An apparatus and method identify a plurality of words to be read, read these selected words during a clock latency period, and then shift these words out synchronously at an end of the latency period. In another aspect of the present invention, the above method of reading a plurality of words during a clock latency period and shifting them out synchronously after the latency period is facilitated by a two tier column decoder. The two-tier column decoder has two decoders. A first-tier decoder decodes a first group of words to be read during the latency period, and a second-tier decoder decodes subsequent words to be shifted out synchronously during a burst period.

Abstract: A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.

Abstract: A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.

Abstract: An apparatus and method identify a plurality of words to be read, read these selected words during a clock latency period, and then shift these words out synchronously at an end of the latency period. In another aspect of the present invention, the above method of reading a plurality of words during a clock latency period and shifting them out synchronously after the latency period is facilitated by a two tier column decoder. The two-tier column decoder has two decoders. A first-tier decoder decodes a first group of words to be read during the latency period, and a second-tier decoder decodes subsequent words to be shifted out synchronously during a burst period.

Abstract: A page buffer facilitates programming of a memory cell within an associated memory array by selectively connecting a bit line associated with the memory cell to a negative voltage supply in response to the logic state of a data signal. The page buffer includes an SRAM latch having first and second nodes, a cross-coupled latch having first and second nodes, and a pass transistor. The first node of the SRAM latch is coupled to receive the data signal and to a first control terminal of the cross-coupled latch. The second node of the SRAM latch is coupled to a second control terminal of the cross-coupled latch. The second node of the cross-coupled latch is coupled to a gate of the pass transistor which, in turn, is connected between the bit line and the negative voltage supply. When the data signal is in a first logic state, the cross-coupled latch turns on the pass transistor and, in connecting the bit line to the negative voltage supply, facilitates programming of the cell.

Abstract: A nonvolatile memory array is disclosed which includes a plurality of PMOS two-transistor (2T) memory cells. Each 2T cell includes a PMOS floating gate transistor and a PMOS select transistor and is connected between a bit line and a common source line. The select gate and the control gate of each 2T cell in a common row are connected to a word line and to a control gate line, respectively. The 2T cells of the array are programmed using a combination of FN tunneling and BTBT induced hot electron injection, and are erased using FN tunneling. In some embodiments, the array is divided into sectors, where each sector is defined by an n- well region and includes a predetermined number of rows of the 2T cells. Here, the source of each 2T cell in a sector is coupled to a common source line of the sector. In other embodiments, the bit lines of the array are segmented along sector boundaries.

Abstract: A charge pump circuit including N stages of diode-capacitor voltage multipliers clocked so as to convert a low voltage received from a supply voltage to a high voltage at an output terminal thereof employs an output stage to improve the efficiency of the charge pump. The output stage includes first and second legs each coupled to the output terminal, where the first leg provides current to the output terminal during low transitions of the clock signal and the second leg provides current to the output terminal during high transitions of the clock signal. In some embodiments, numerous ones of the above-mentioned charge pump circuit may be connected in parallel to achieve even greater output currents. Thus, unlike conventional charge pump circuits, a substantially constant current is provided to the output terminal throughout each period of the clock signal, thereby increasing the average total current provided to the output terminal and, thus, increasing the driving capability of the charge pump circuit.

Abstract: A semiconductor memory includes a plurality of memory cells and a corresponding plurality of page buffers. When writing to a selected row of cells, input data is first latched into the page buffers. The cells in the selected row are then programmed according to the data latched within the page buffers. After programming, data stored in the cells is forwarded to the corresponding page buffers. If, for each cell, the data stored in the cell matches the data latched in its corresponding page buffer, the page buffer is reset. The selected row of cells are subsequently re-programmed, whereby only cells corresponding to those page buffers which have not been reset are re-programmed. In this manner, cells properly programmed during the first program operation are not re-programmed during program verify operations.

Abstract: The frequency of a clocking signal is adjusted in response to fluctuations in the power supply voltage. In one embodiment, a control circuit has a plurality of clock input terminals each coupled between selected adjacent ones of the stages of a multiple-stage ring oscillator circuit and has an output clock terminal coupled to an input terminal of the ring oscillator circuit. In this manner, the control circuit may implement a plurality of loops each including a different variety of the stages of the ring oscillator circuit, wherein the clocking signal associated with each of the loops has a unique frequency. A plurality of trip voltages each being equal to a unique predetermined fraction of the power supply voltage are compared to a reference voltage. The control circuit selects, in response to the comparison of the trip voltages and the reference voltage, one of the loops mentioned above to provide its clocking signal to an output terminal of the oscillator.

Abstract: A sensing circuit charges the bit lines of an associated memory array using one or more large-area pass transistors during reading operations of a selected memory cell of the memory array. In this manner, the read speed of the memory array is independent of the channel current of the memory cell. A sink transistor sinks a constant current from the selected bit line during reading to improve the noise margin of the sensing circuit so that memory arrays associated with the sensing circuit do not require the reference bit lines.

Abstract: A row decoder circuit selectively provides suitable programming, reading, and erasing voltages to an associated memory array employing PMOS floating gate transistors as memory cells. In some embodiments, during programming, the row decoder circuit pulls a selected word line of the associated memory array high to a programming voltage on a first voltage line and maintains an un-selected word line at a predetermined potential. During reading, the row decoder circuit discharges the word line, if selected, to ground potential, and maintains the word line, if un-selected, at a predetermined potential. During erasing, the row decoder circuit charges the word line to a high negative voltage. The row decoder circuit includes isolation means to electrically isolate the word line of the associated memory array from undesirable potentials during programming, reading, and erasing operations.

Abstract: A non-volatile memory latch device includes two PMOS memory cells and a cross-coupled static latch having two PMOS transistors and two NMOS transistors. The floating gates of each PMOS memory cell/transistor pair are coupled together. The control gates of all four PMOS devices are commonly connected to an input. The latch is programmed by applying -3 to -8 volts to the drain of one of the PMOS memory cells, floating the drain of the other PMOS memory cell, and applying 7 to 11 volts to the control gates of all four PMOS devices. The latch is erased by applying 3 to 8 volts to both drains of the PMOS memory cells and -7 to -11 volts to the control gates of all four PMOS devices. Lower programming and erasing voltages are possible with the PMOS latch, as compared with conventional NMOS latches.