Abstract: A storage module may include a controller configured to communicate with a memory having a plurality of memory dies. The controller may include a plurality of bond pads, where each bond pad is configured to communicate a same type of memory signal, and where each bond pad is electrically connected to at least one but less than all of the plurality of memory dies. A core of the controller may identify a memory die that it wants to communicate a memory signal and an associated bond pad with which to communicate the memory signal.

Abstract: Methods and apparatuses for applying different voltages to an I/O interface (such as to the pads of the I/O interface) and determining the data integrity of communicating data (either transmitting to or receiving data from) to another device is disclosed. Data integrity may be measured in one of several ways, such as the window (or timing) at which data can be transmitted correctly using the different voltages. The determined data integrity may be compared with a minimum data integrity, such as a minimum window. In the event that the determined data integrity is greater or better than the minimum data integrity, then the voltage may be reduced and the data integrity determination may be performed again. In this way, the voltage applied to the I/O interface may be reduced while still meeting the minimum data integrity requirements.

Abstract: Methods and apparatuses for applying different voltages to an I/O interface (such as to the pads of the I/O interface) and determining the data integrity of communicating data (either transmitting to or receiving data from) to another device is disclosed. Data integrity may be measured in one of several ways, such as the window (or timing) at which data can be transmitted correctly using the different voltages. The determined data integrity may be compared with a minimum data integrity, such as a minimum window. In the event that the determined data integrity is greater or better than the minimum data integrity, then the voltage may be reduced and the data integrity determination may be performed again. In this way, the voltage applied to the I/O interface may be reduced while still meeting the minimum data integrity requirements.

Abstract: The timing and power consumption of controller circuits are is dependent on Process, Voltage, and Temperature. If the controller ASIC can measure the average voltage level during run-time, then firmware can use this information to tune the voltages for optimal speed/power performance. A voltage detector generates an output of, for example, 3 bits, where each state of the three bit bus represents a voltage band. These bits can then be used by the firmware to trim the appropriate regulators to boost/lower the voltages. This can be done for both the core voltage and I/O voltages. The firmware can be further optimized to take into account the states of temperature detectors and process detectors along with voltage band detector to optimize the system performance.

Abstract: A storage module may include a controller configured to communicate with a memory having a plurality of memory dies. The controller may include a plurality of bond pads, where each bond pad is configured to communicate a same type of memory signal, and where each bond pad is electrically connected to at least one but less than all of the plurality of memory dies. A core of the controller may identify a memory die that it wants to communicate a memory signal and an associated bond pad with which to communicate the memory signal.