Abstract: A two-step, hybrid analog-to-digital converter (ADC) includes a Delta-Sigma ADC that employs chopping to resolve MSBs, a Nyquist ADC that employs correlated double sampling (CDS) to resolve LSBs, and a combiner that combines the MSBs and the LSBs to generate a digital output signal. The Delta-Sigma ADC has first and second integrators where, after resolving the MSBs, the first integrator is re-configured to function as a reference buffer for the Nyquist ADC and the second integrator is re-configured to function as the Nyquist ADC.

Abstract: A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.

Abstract: A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.

Abstract: A method of trimming a current source in an IC includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip ADC is used to provide corresponding digital reference and digital measurement signals. A digital comparator compares the digital signals and provides a digital trim signal, which is used to adjust the current to be trimmed until the digital measurement signal is equal to the digital reference signal within an acceptable tolerance. Gain and offset errors in the ADC cancel and do not affect the calibration of the trim operation.

Abstract: A method of trimming a current source in an IC includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip ADC is used to provide corresponding digital reference and digital measurement signals. A digital comparator compares the digital signals and provides a digital trim signal, which is used to adjust the current to be trimmed until the digital measurement signal is equal to the digital reference signal within an acceptable tolerance. Gain and offset errors in the ADC cancel and do not affect the calibration of the trim operation.

Abstract: A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.

Abstract: A SAR ADC includes capacitors, a comparator, and a SAR logic circuit. The capacitors include a first set of capacitors and an error-detection capacitor. The first set of capacitors generates a first set of voltage signals that are compared with a common-mode voltage signal (VCM) by the comparator during a first set of comparison cycles. The comparator generates a first set of control signals that is used by the SAR logic circuit to successively approximate the first set of voltage signals and generate a first set of bits. An error-detection capacitor generates an error-detection signal that is compared with the common-mode voltage signal VCM by the comparator to generate an error-detection control signal. The SAR logic circuit compensate for an error in the first set of bits based the logic state of the error-detection control signal.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.

Abstract: A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.

Abstract: An aspect of the invention improves accuracy of digital codes generated at the output of a SAR ADC by using multiple reference voltages. A first reference voltage is used to generate an equivalent voltage corresponding to previous resolved bits and a second reference voltage is used to generate equivalent voltage corresponding to the bits being presently resolved. Another aspect of the present invention provides an ADC with high SNR as well as high throughput performance. Such a feature may be achieved by resolving some of the MSBs of the digital code using a high speed and low SNR DAC and remaining bits of the digital code using a high SNR DAC.