Abstract: Mechanisms, in a data processing system comprising a first adapter and second adapter, for performing a failover operation from the first adapter to the second adapter are provided. The mechanisms detect that an imminent failure of the first adapter is likely to occur and initiate a failover priming operation in the first adapter and second adapter in response to detecting the imminent failure. The failover priming operation configures ingress and egress buffers of the second adapter to have a similar configuration to ingress and egress buffers of the first adapter. The mechanisms migrate processing of ingress data traffic to the second adapter prior to failure of the first adapter such that the first adapter processes egress data traffic from the data processing system and the second adapter processes ingress data traffic to the data processing system.

Abstract: Mechanisms, in a data processing system comprising a first adapter and second adapter, for performing a failover operation from the first adapter to the second adapter are provided. The mechanisms detect that an imminent failure of the first adapter is likely to occur and initiate a failover priming operation in the first adapter and second adapter in response to detecting the imminent failure. The failover priming operation configures ingress and egress buffers of the second adapter to have a similar configuration to ingress and egress buffers of the first adapter. The mechanisms migrate processing of ingress data traffic to the second adapter prior to failure of the first adapter such that the first adapter processes egress data traffic from the data processing system and the second adapter processes ingress data traffic to the data processing system.

Abstract: In response to receiving a request for a DMA data transfer, a DMA transfer mode may be determined based on based on the size of the requested DMA data transfer and profile data of an I/O adapter. The profile data for the I/O adapter may include a physical location of the I/O adapter or a number of clients supported by the I/O adapter. The DMA transfer mode may also be determined based on a preference of an application or an I/O device. Moreover, the DMA transfer mode may be determined based on a CPU usage metric being outside of a threshold for the CPU usage metric or on a memory usage metric being outside of a threshold for the memory usage metric.

Abstract: An approach is provided that collects data from a multi-function adapter that is used by multiple functions. In the approach, a master function is dynamically selected from the group of functions. The approach further allows the master function to perform a disruptive adapter data collection while inhibiting performance of disruptive adapter data collection processes by the other (non-master) functions.

Abstract: A method and technique for updating firmware on a multi-protocol network adapter includes: reading parameter values for a firmware update to determine an update scope indicating one or more functions of the network adapter affected by the firmware update and a write scope indicating which of the one or more functions should receive a write request for writing the firmware update to the network adapter. The update tool is operable to: send a message indicating to the one or more functions based on the update scope that a firmware update process is beginning; send a write request to write the firmware update to the one or more functions based on the write scope; send a reset request to reset the one or more functions to activate the firmware update; and send a message indicating to the one or more functions that the firmware update process is completed.

Abstract: Mechanisms are provided for providing an early warning of an error state of a remote direct memory access (RDMA) resource to a userspace application. The mechanisms detect, using kernelspace logic, an error event having occurred, and perform a write operation to write an error state value to a userspace shared memory state data structure indicating the RDMA resource to be in an error state. The mechanisms detect, using userspace logic, the RDMA resource being in an error state by reading the error state value from the userspace shared memory state data structure in response to a userspace application attempting to perform a RDMA operation using the RDMA resource. In addition, the mechanisms initiate, by the userspace application, an operation to tear down the RDMA resource in response to detecting the RDMA resource being in the error state.

Abstract: Mechanisms are provided for generating a system dump data structure based on device state data. A system dump operation is initialized in a data processing system and a device dump is requested by a dump manager from a device coupled to the data processing system. A collection scope data structure and disruption vector corresponding to the device are retrieved. The collection scope data structure specifies a set of one or more functions in the device for which to collect state data. The disruption vector specifies, for each of the one or more functions, a corresponding level of disruption that will be caused by the device dump. The device dump data is collected from the device in accordance with the collection scope data structure and the disruption vector and the system dump data structure is generated based on the collected device dump data.

Abstract: Mechanisms are provided for providing an early warning of an error state of a remote direct memory access (RDMA) resource to a userspace application. The mechanisms detect, using kernelspace logic, an error event having occurred, and perform a write operation to write an error state value to a userspace shared memory state data structure indicating the RDMA resource to be in an error state. The mechanisms detect, using userspace logic, the RDMA resource being in an error state by reading the error state value from the userspace shared memory state data structure in response to a userspace application attempting to perform a RDMA operation using the RDMA resource. In addition, the mechanisms initiate, by the userspace application, an operation to tear down the RDMA resource in response to detecting the RDMA resource being in the error state.

Abstract: Mechanisms are provided for providing an early warning of an error state of a remote direct memory access (RDMA) resource to a userspace application. The mechanisms detect, using kernelspace logic, an error event having occurred, and perform a write operation to write an error state value to a userspace shared memory state data structure indicating the RDMA resource to be in an error state. The mechanisms detect, using userspace logic, the RDMA resource being in an error state by reading the error state value from the userspace shared memory state data structure in response to a userspace application attempting to perform a RDMA operation using the RDMA resource. In addition, the mechanisms initiate, by the userspace application, an operation to tear down the RDMA resource in response to detecting the RDMA resource being in the error state.

Abstract: Mechanisms are provided for providing an early warning of an error state of a remote direct memory access (RDMA) resource to a userspace application. The mechanisms detect, using kernelspace logic, an error event having occurred, and perform a write operation to write an error state value to a userspace shared memory state data structure indicating the RDMA resource to be in an error state. The mechanisms detect, using userspace logic, the RDMA resource being in an error state by reading the error state value from the userspace shared memory state data structure in response to a userspace application attempting to perform a RDMA operation using the RDMA resource. In addition, the mechanisms initiate, by the userspace application, an operation to tear down the RDMA resource in response to detecting the RDMA resource being in the error state.

Abstract: In response to receiving a request for a DMA data transfer, a DMA transfer mode may be determined based on based on the size of the requested DMA data transfer and profile data of an I/O adapter. The profile data for the I/O adapter may include a physical location of the I/O adapter or a number of clients supported by the I/O adapter. The DMA transfer mode may also be determined based on a preference of an application or an I/O device. Moreover, the DMA transfer mode may be determined based on a CPU usage metric being outside of a threshold for the CPU usage metric or on a memory usage metric being outside of a threshold for the memory usage metric.

Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.

Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.

Abstract: In a method of handling errors in a digital system that includes a root complex in data communication with at least one endpoint, the endpoint including at least one advanced error reporting register, an error is detected by the endpoint. Error data indicative of the error is stored in an advanced error reporting register. An indication of which transaction caused the error is stored in a secondary location. An error message packet that includes the error data and the indication of which transaction caused the error is generated. The error message packet is transmitted to the root complex. The root complex is caused to take a preselected action in response to the error message packet.

Abstract: In a method of handling errors in a digital system that includes a root complex in data communication with at least one endpoint, the endpoint including at least one advanced error reporting register, an error is detected by the endpoint. Error data indicative of the error is stored in an advanced error reporting register. An indication of which transaction caused the error is stored in a secondary location. An error message packet that includes the error data and the indication of which transaction caused the error is generated. The error message packet is transmitted to the root complex. The root complex is caused to take a preselected action in response to the error message packet.

Abstract: Methods, systems, and products are disclosed for operating Peripheral Component Interconnect (‘PCI’) Express resources in a logically partitioned computing system that include: allocating, by a hypervisor installed on the computing system, a PCI Express adapter installed in the computing system to a logical partition of the computing system, including establishing a data communication path between a processor of the computing system and the PCI Express adapter, the data communication path including a link between a PCI Express root complex and the PCI Express adapter; and administering, by the hypervisor for the logical partition, the PCI Express root complex and the link between the PCI Express root complex and the PCI Express adapter.

Abstract: Methods, systems, and products are disclosed for operating Peripheral Component Interconnect (‘PCI’) Express resources in a logically partitioned computing system that include: allocating, by a hypervisor installed on the computing system, a PCI Express adapter installed in the computing system to a logical partition of the computing system, including establishing a data communication path between a processor of the computing system and the PCI Express adapter, the data communication path including a link between a PCI Express root complex and the PCI Express adapter; and administering, by the hypervisor for the logical partition, the PCI Express root complex and the link between the PCI Express root complex and the PCI Express adapter.

Abstract: A method, apparatus, and computer instructions for generating a hardware interrupt to the operating system in response to detecting a presence of the event in the platform. The event is stored in a partition queue associated with a partition firmware in response to the presence of the event. The event is identified in the partition queue, in response to receiving a request to check the hardware interrupt in the partition firmware. The event is processed in response to identifying the event.

Abstract: A method, apparatus, and computer instructions for generating a hardware interrupt to the operating system in response to detecting a presence of the event in the platform. The event is stored in a partition queue associated with a partition firmware in response to the presence of the event. The event is identified in the partition queue, in response to receiving a request to check the hardware interrupt in the partition firmware. The event is processed in response to identifying the event.

Abstract: A method, apparatus, and computer instructions for updating partition firmware in a logical partitioned data processing system. A first module in the partition firmware for a partition within a set of partitions is loaded. The first module provides an interface for receiving calls from an operating system in the partition. A second module in the partition firmware for the partition is loaded. The second module is loaded by the first module, and the second module provides a plurality of functions. Calls received at the interface of the first module are routed to the second module. The second module executes functions in response to the calls. A new second module may be loaded while the original second module continues to execute. Thereafter, the new second module may begin execution with the original second module being terminated.