Patents by Inventor Viktor I. Koldiaev
Viktor I. Koldiaev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170186882Abstract: The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches.Type: ApplicationFiled: December 12, 2016Publication date: June 29, 2017Inventors: Viktor I. Koldiaev, Rimma A. Pirogova
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Patent number: 9520501Abstract: The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches.Type: GrantFiled: June 3, 2015Date of Patent: December 13, 2016Assignee: FinScale Inc.Inventors: Viktor I. Koldiaev, Rimma A. Pirogova
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Publication number: 20150279997Abstract: The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches.Type: ApplicationFiled: June 3, 2015Publication date: October 1, 2015Inventors: Viktor I. Koldiaev, Rimma A. Pirogova
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Patent number: 9093311Abstract: Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: GrantFiled: June 9, 2014Date of Patent: July 28, 2015Assignee: Micron Technology, Inc.Inventors: Michael A. Van Buskirk, Christian Caillat, Viktor I. Koldiaev, Jungtae Kwon, Pierre C. Fazan
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Publication number: 20140291763Abstract: Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: ApplicationFiled: June 9, 2014Publication date: October 2, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael A. VAN BUSKIRK, Christian CAILLAT, Viktor I. KOLDIAEV, Jungtae KWON, Pierre C. FAZAN
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Patent number: 8817534Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.Type: GrantFiled: May 21, 2013Date of Patent: August 26, 2014Assignee: Micron Technology, Inc.Inventors: Serguei Okhonin, Viktor I Koldiaev, Mikhail Nagoga, Yogesh Luthra
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Patent number: 8748959Abstract: A semiconductor memory device is disclosed. In one particular exemplary embodiment, the semiconductor memory device includes a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation and a second barrier wall extending in the second orientation and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: GrantFiled: March 31, 2010Date of Patent: June 10, 2014Assignee: Micron Technology, Inc.Inventors: Michael A. Van Buskirk, Christian Caillat, Viktor I Koldiaev, Jungtae Kwon, Pierre C. Fazan
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Publication number: 20130250699Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.Type: ApplicationFiled: May 21, 2013Publication date: September 26, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Serguei OKHONIN, Viktor I. KOLDIAEV, Mikhail NAGOGA, Yogesh LUTHRA
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Patent number: 8537610Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.Type: GrantFiled: July 12, 2010Date of Patent: September 17, 2013Assignee: Micron Technology, Inc.Inventors: Serguei Okhonin, Viktor I Koldiaev, Mikhail Nagoga, Yogesh Luthra
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Publication number: 20110007578Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.Type: ApplicationFiled: July 12, 2010Publication date: January 13, 2011Applicant: Innovative Silicon ISi SAInventors: Serguei Okhonin, Viktor I. Koldiaev, Mikhail Nagoga, Yogesh Luthra
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Publication number: 20100259964Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: ApplicationFiled: March 31, 2010Publication date: October 14, 2010Applicant: Innovative Silicon ISi SAInventors: Michael A. Van Buskirk, Christian Caillat, Viktor I. Koldiaev, Jungtae Kwon, Pierre C. Fazan