Patents by Inventor Vimal S. Parikh

Vimal S. Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8432406
    Abstract: An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit that is configured to produce and issue ni initial outputs based on execution of a set of clipping operations, wherein ni represents the number of the initial outputs that are issued by the clipping unit prior to context switching, and the initial outputs partially define a clipped graphics primitive. The graphics processing apparatus also includes a control unit connected to the clipping unit. The control unit is configured to preserve an initial execution state of the clipping unit in response to an initial command for context switching, wherein the initial execution state is preserved based on ni.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: April 30, 2013
    Assignee: NVIDIA Corporation
    Inventors: Lordson L. Yue, Vimal S. Parikh
  • Patent number: 8139071
    Abstract: An apparatus and method for buffering graphics data are described. In one embodiment, a graphics processing apparatus includes a storage unit and a reorder control unit that is connected to the storage unit. The reorder control unit is configured to coordinate storage of vertex attributes in the storage unit so as to convert the vertex attributes from an initial order to a modified order. The reorder control unit is configured to identify a subset of the vertex attributes to be stored within a common range of addresses in the storage unit, and the reorder control unit is configured to access the storage unit such that the subset of the vertex attributes is written into the storage unit substantially in parallel.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: March 20, 2012
    Assignee: Nvidia Corporation
    Inventors: Andrew J. Tao, Vimal S. Parikh, Yan Yan Tang
  • Patent number: 7999817
    Abstract: An apparatus and method for buffering graphics data are described. In one embodiment, a graphics processing apparatus includes a memory and a buffering unit that is connected to the memory. The buffering unit is configured to buffer vertex attributes en route to the memory. The buffering unit is configured to coalesce a subset of the vertex attributes to be stored within a common range of addresses in the memory, and the buffering unit is configured to issue a single write request to the memory on behalf of the subset of the vertex attributes.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: August 16, 2011
    Assignee: NVIDIA Corporation
    Inventors: Andrew J. Tao, Vimal S. Parikh, Yan Yan Tang
  • Patent number: 7714877
    Abstract: An apparatus, system, and method for determining clipping distances are described. In one embodiment, a graphics processing apparatus includes a clipping unit and an instruction memory connected to the clipping unit. The instruction memory includes a clipping program to direct the clipping unit to perform clipping operations. The clipping program includes a clipping distance instruction to determine a clipping distance with respect to any of a set of clipping planes.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: May 11, 2010
    Assignee: Nvidia Corporation
    Inventors: Vimal S. Parikh, Lordson L. Yue
  • Patent number: 7705845
    Abstract: Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping engine and an output unit connected to the clipping engine. The clipping engine is configured to clip an input graphics primitive with respect to a set of clipping planes to derive spatial attributes of new vertices. The output unit is configured to identify a subset of the new vertices that defines an output graphics primitive, and the output unit is configured to derive non-spatial attributes of the subset of the new vertices to produce the output graphics primitive.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: April 27, 2010
    Assignee: NVIDIA Corporation
    Inventors: Vimal S. Parikh, Henry Packard Moreton, Andrew J. Tao
  • Patent number: 7616218
    Abstract: Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a clipping module includes a clipping engine and a clipping controller connected to the clipping engine. The clipping controller is configured to determine which edges of an input graphics primitive intersect a first clipping plane. The clipping controller is configured to direct the clipping engine to clip, with respect to the first clipping plane, a first pair of edges of the input graphics primitive in response to determining that the first pair of edges intersect the first clipping plane.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: November 10, 2009
    Assignee: NVIDIA Corporation
    Inventors: Vimal S. Parikh, Andrew J. Tao, Lordson L. Yue
  • Patent number: 7542046
    Abstract: An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit, a read-only memory that is connected to the clipping unit, a read-write memory that is connected to the clipping unit, and an addressing unit that is connected to the read-only memory and the read-write memory. The read-only memory is configured to store a clipping program, and the read-write memory is configured to store a patch program. The addressing unit is configured to selectively address one of the read-only memory and the read-write memory based on a set of input conditions.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: June 2, 2009
    Assignee: Nvidia Corporation
    Inventors: Lordson L. Yue, Vimal S. Parikh, Andrew J. Tao
  • Patent number: 7466322
    Abstract: Vertices defining a graphics primitive are converted into homogeneous space and clipped against a single clipping plane, the w=0 plane, to produce a clipped graphics primitive having vertices including w coordinates that are greater than or equal to zero. Rasterizing a graphics primitive having a vertex with a w coordinates that is greater than or equal to zero is less complex than rasterizing a graphics primitive having a vertex with a w coordinate that is less than zero. Clipping against the w=0 plane is less complex than conventional clipping since conventional clipping may require that the graphics primitive be clipped against each of the six faces of the viewing frustum to produce a clipped graphics primitive.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: December 16, 2008
    Assignee: NVIDIA Corporation
    Inventors: Henry P. Moreton, Vimal S. Parikh, Andrew J. Tao
  • Patent number: 7439988
    Abstract: Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a clipping module includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation that is defined with respect to a clipping plane. The clipping engine is configured to clip the graphics primitive with respect to the clipping plane based on the canonical representation.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: October 21, 2008
    Assignee: Nvidia Corporation
    Inventors: Vimal S. Parikh, Henry Packard Moreton, Lordson L. Yue
  • Patent number: 7420572
    Abstract: An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit that is configured to issue an initial set of outputs based on execution of a set of clipping operations. The graphics processing apparatus also includes a control unit that is connected to the clipping unit. The control unit is configured to preserve an initial execution state of the clipping unit in response to an initial command for context switching, and the initial execution state is preserved based on a number of the initial set of outputs.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: September 2, 2008
    Assignee: NVIDIA Corporation
    Inventors: Lordson L. Yue, Vimal S. Parikh
  • Patent number: 7292242
    Abstract: Clipping techniques introduce additional vertices into existing primitives without requiring creation of new primitives. For an input triangle with one vertex on the invisible side of a clipping surface, a quadrangle can be defined. The vertices of the quadrangle are the two internal vertices of the input triangle and two clipped vertices. For determining attribute values for pixel shading, three vertices of the quadrangle are selected, and a parameter value for an attribute equation is computed using the three selected vertices. For determining pixel coverage for the quadrangle, the three edges that do not correspond to the edge created by clipping are used.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: November 6, 2007
    Assignee: NVIDA Corporation
    Inventors: Craig M. Wittenbrink, Henry Packard Moreton, Douglas A. Voorhies, John S. Montrym, Vimal S. Parikh
  • Patent number: 7292254
    Abstract: Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation. The clipping engine is configured to perform a set of clipping operations with respect to the canonical representation.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: November 6, 2007
    Assignee: NVIDIA Corporation
    Inventors: Lordson L. Yue, Vimal S. Parikh, Andrew J. Tao
  • Patent number: 6236413
    Abstract: In a computer system including a processor coupled to a memory via a bus, a system for a reduced instruction set graphics processing subsystem. The graphics processing subsystem is configured to accept graphics data from a computer system via a bus. The graphics processing subsystem is deeply pipelined to achieve high bandwidth, and is operable for processing graphics data including a first and second set of graphics instructions. The graphics instructions from the second set are more complex than the graphics instructions from the first set. The graphics processing subsystem also includes a built-in recirculation path for enabling the execution of graphics instructions by multi-pass. The graphics pipeline is streamlined such that the graphics instructions from the first set are processed efficiently. The graphics instructions from the second set are processed by using multi-pass via the recirculation path.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: May 22, 2001
    Assignee: Silicon Graphics, Inc.
    Inventors: Carroll Philip Gossett, Vimal S. Parikh, Nancy Cam Winget