Patents by Inventor Vinay Chenani
Vinay Chenani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923844Abstract: Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.Type: GrantFiled: April 28, 2022Date of Patent: March 5, 2024Assignee: Arm LimitedInventors: Seshagiri Rao Bogi, Vinay Chenani, Gurupadayya Shidaganti, Akshaykumar V Jabi
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Publication number: 20230353150Abstract: Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Inventors: Seshagiri Rao Bogi, Vinay Chenani, Gurupadayya Shidaganti, Akshaykumar V Jabi
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Publication number: 20220038101Abstract: A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.Type: ApplicationFiled: September 15, 2020Publication date: February 3, 2022Applicant: Arm LimitedInventors: Seshagiri Rao Bogi, Gayathri Gandhi, Vinay Chenani, Fabrice Blanc
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Patent number: 11239842Abstract: A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.Type: GrantFiled: September 15, 2020Date of Patent: February 1, 2022Assignee: Arm LimitedInventors: Seshagiri Rao Bogi, Gayathri Gandhi, Vinay Chenani, Fabrice Blanc
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Patent number: 11169590Abstract: Various implementations described herein are directed to a device having an output pad that provides an input-output (IO) voltage from an IO power supply. The device may include core ramp detection circuitry that detects a first ramp of a core voltage from a core power supply and provides a core ramp sensing signal. The device may include output logic circuitry that couples the output pad to ground after receiving the core ramp sensing signal so as to reduce leakage of the IO power supply.Type: GrantFiled: July 19, 2019Date of Patent: November 9, 2021Assignee: Arm LimitedInventors: Ranabir Dey, Vinay Chenani, Kundan Srivastava, Vijaya Kumar Vinukonda
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Publication number: 20210018974Abstract: Various implementations described herein are directed to a device having an output pad that provides an input-output (IO) voltage from an IO power supply. The device may include core ramp detection circuitry that detects a first ramp of a core voltage from a core power supply and provides a core ramp sensing signal. The device may include output logic circuitry that couples the output pad to ground after receiving the core ramp sensing signal so as to reduce leakage of the IO power supply.Type: ApplicationFiled: July 19, 2019Publication date: January 21, 2021Inventors: Ranabir Dey, Vinay Chenani, Kundan Srivastava, Vijaya Kumar Vinukonda
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Patent number: 10784842Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.Type: GrantFiled: January 3, 2019Date of Patent: September 22, 2020Assignee: Arm LimitedInventors: Seshagiri Rao Bogi, Vinay Chenani, Biswanath Nayak, Vijaya Kumar Vinukonda
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Publication number: 20200220529Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.Type: ApplicationFiled: January 3, 2019Publication date: July 9, 2020Inventors: Seshagiri Rao Bogi, Vinay Chenani, Biswanath Nayak, Vijaya Kumar Vinukonda