Abstract: A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block. The processing device converts a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a neighboring plane of the memory device from that of the first block. The processing device converts a media endurance metric value of the second block from SLC-type to MLC-type.

Abstract: Methods, systems, and devices for block conversion to preserve memory capacity are described. A device may perform a quantity of one or more access operations on a block that includes a set of memory cells configured as single-level cells each of which is configured for storing multiple bits. After performing the quantity of one or more access operations on the block the device may convert the set of memory cells from single-level cells into multiple-level cells configured for storing multiple bits. The device may then determine a remaining quantity of access operations permitted to be performed on the block and operate the bloc based on the remaining quantity of access operations.

Abstract: Methods, apparatus and systems for data storage devices that include non-volatile memory (NVM) are described. One such apparatus includes a non-volatile memory, a data storage device controller configured to receive a command from a host device, and wherein the data storage device controller comprises a file system analyzer comprising a determination circuit configured to determine based on the command from the host device whether a logical block address (LBA) referenced in the command is part of a known file extent, and a selection circuit configured to select a flash translation layer (FTL) workflow for the file extent in response to the determination that the LBA referenced in the command is part of the known file extent.

Abstract: A storage device includes a storage controller, non-volatile memory, volatile memory and a communication interface configured to connect to external volatile memory of a host system. The storage controller is configured to receive data from the host system for storing in the non-volatile memory, buffer the data in the volatile memory, obtain parity data corresponding to the buffered data from an external volatile memory within the host system, compute XOR parity data for the buffered data based on the parity data and the buffered data, store the computed XOR parity data on the external volatile memory, and write the data from the host to the non-volatile memory.

Abstract: A storage device includes a storage controller, non-volatile memory, volatile memory and a communication interface configured to connect to external volatile memory of a host system. The storage controller is configured to receive data from the host system for storing in the non-volatile memory, buffer the data in the volatile memory, obtain parity data corresponding to the buffered data from an external volatile memory within the host system, compute XOR parity data for the buffered data based on the parity data and the buffered data, store the computed XOR parity data on the external volatile memory, and write the data from the host to the non-volatile memory.

Abstract: Methods, apparatus and systems for data storage devices that include non-volatile memory (NVM) are described. One such apparatus includes a non-volatile memory, a data storage device controller configured to receive a command from a host device, and wherein the data storage device controller comprises a file system analyzer comprising a determination circuit configured to determine based on the command from the host device whether a logical block address (LBA) referenced in the command is part of a known file extent, and a selection circuit configured to select a flash translation layer (FTL) workflow for the file extent in response to the determination that the LBA referenced in the command is part of the known file extent.

Abstract: Apparatuses, systems, and methods are disclosed for error characterization for control of non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to acquire an error characterization for a region of memory. Also, an error characterization may comprise information about one or more types of errors to which a region of memory is susceptible. A controller may be configured to assign a region of memory into a logical group based on an error characterization. Further, a logical group may comprise a plurality of regions of memory. Additionally, a controller may be configured to service a write request by striping data across multiple regions assigned to a logical group.

Abstract: An example of a system includes a host interface, a set of non-volatile memory cells assigned a first logical address range, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits are configured to generate debug data and send the debug data through the host interface in response to a command received through the host interface. The command is directed to a second logical address range, the second logical address range assigned exclusively for debug data.

Abstract: Apparatuses, systems, and methods are disclosed for error characterization for control of non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to acquire an error characterization for a region of memory. Also, an error characterization may comprise information about one or more types of errors to which a region of memory is susceptible. A controller may be configured to assign a region of memory into a logical group based on an error characterization. Further, a logical group may comprise a plurality of regions of memory. Additionally, a controller may be configured to service a write request by striping data across multiple regions assigned to a logical group.

Abstract: An example of a system includes a host interface, a set of non-volatile memory cells assigned a first logical address range, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits are configured to generate debug data and send the debug data through the host interface in response to a command received through the host interface. The command is directed to a second logical address range, the second logical address range assigned exclusively for debug data.