Abstract: A data storage system includes a storage medium including a plurality of memory cells; a storage controller in communication with the storage medium; and an electrical interface between the storage medium and the storage controller. The electrical interface includes an N-bit data bus; a data strobe; a command latch enable signal; and an address latch enable signal; wherein, while the command latch signal or the address latch enable signal is asserted, the storage medium is configured to: (i) receive command or address data via a subset of lines of the data bus; and (ii) latch the command or address data using the data strobe.

Abstract: A data storage system includes a storage medium including a plurality of memory cells; a storage controller in communication with the storage medium; and an electrical interface between the storage medium and the storage controller. The electrical interface includes an N-bit data bus; a data strobe; a command latch enable signal; and an address latch enable signal; wherein, while the command latch signal or the address latch enable signal is asserted, the storage medium is configured to: (i) receive command or address data via a subset of lines of the data bus; and (ii) latch the command or address data using the data strobe.

Abstract: A data storage system includes a storage medium including plurality of memory cells, a storage controller in communication with the storage medium, an electrical interface circuitry configured to pass data via a channel disposed between the storage medium and the storage controller; and voltage training circuitry configured to train a high-level output voltage (VOH) for each of a plurality of data lines of the channel. Training the VOH includes, for each of the plurality of data lines of the channel, calibrating a pull-up driver of the storage controller against an on-die termination circuit of the storage medium, calibrating a pull-down driver of the storage controller against the pull-up driver of the storage controller, and calibrating an on-die termination circuit of the storage controller against a pull-up driver of the storage medium.

Abstract: A circuit comprising a non-volatile memory array, an Input/Output (IO) circuit, a decoder circuit, a control circuit, and a read/write circuit. The non-volatile memory array couples to an address decoder that identifies a location within the non-volatile memory array for a storage command. The IO circuit couples to a decoder circuit through a control bus. The decoder circuit decodes a command address and storage command from a fixed length command sequence received by the IO circuit over the data bus. The decoder circuit may include a serial-in parallel out (SIPO) circuit for decoding and parallel operation. The control circuit couples to the IO and decoder circuits and generates control signals to execute decoded storage commands. The read/write circuit couples to the non-volatile memory array and the control circuit. The read/write circuit transfers data between the non-volatile memory array and the IO circuit in response to the storage commands.

Abstract: A memory device includes a memory controller to transmit or receive input/output (“I/O”) data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a memory module communicably coupled to the memory controller. The memory module receives the command data, address data, or parameter data from the memory controller to perform an operation.

Abstract: A memory device includes a memory controller to transmit or receive input/output (“I/O”) data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a memory module communicably coupled to the memory controller. The memory module receives the command data, address data, or parameter data from the memory controller to perform an operation.

Abstract: A memory device includes receiving, by a memory module, a first combined signal and a second combined signal from a memory controller and decoding, by the memory module, the first combined signal and the second combined signal to obtain a first chip enable signal, a first address latch enable signal, and a first command latch enable signal. Upon decoding, the first command latch enable signal and the first address latch enable signal are received substantially simultaneously as the first chip enable signal to reduce a setup time.

Abstract: A memory device includes receiving, by a memory module, a first combined signal and a second combined signal from a memory controller and decoding, by the memory module, the first combined signal and the second combined signal to obtain a first chip enable signal, a first address latch enable signal, and a first command latch enable signal. Upon decoding, the first command latch enable signal and the first address latch enable signal are received substantially simultaneously as the first chip enable signal to reduce a setup time.

Abstract: This disclosure provides techniques for debugging a computing system in a post-silicon validation process. In one example, a system can include a memory storing a set of instructions. The system can include a controller configured to fetch and execute the set of instructions. The system can include a logic block. The system can include a control bus coupling the memory, the controller, and the logic block. The control bus can include a first break-in circuit and a second break-in circuit each coupled to the controller. The first break-in circuit and the second break-in circuit can be configured to selectively cascade a break point from the controller through the logic block to halt execution of the set of instructions.

Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

Abstract: A memory device includes an electrical line operably coupled to a plurality of memory cells, and a switchable impedance driver operably coupled to the electrical line. An electronic circuit includes a first driver having a first output impedance, and a second driver having a second output impedance that is less than the first output impedance. The first driver and the second driver are operably coupled in parallel to an output of the electronic circuit. The electronic circuit includes logic circuitry to enable the second driver during switching of a digital output of the driver. A method includes driving an output with both the first driver and the second driver when an input switches between logic levels, and disabling the second driver when the output reaches a desired logic level following the switch between logic levels of the input.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

Abstract: An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being cascaded and coupled to the node. The node is defined between the first capacitor and the second capacitor. A pad is coupled to the node. The first bias circuit maintains a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit maintains the voltage at the node below the threshold during the receive mode. The voltage at the node is dependent on a voltage at the pad during the receive mode.

Abstract: An input/output (IO) circuit is provided that reduces stress on a driver without using an additional reference voltage. The IO circuit receives an overshoot voltage and an undershoot voltage in a receive mode. The IO circuit includes a driver circuit. The driver circuit includes an NMOS transistor coupled to a PMOS transistor. A pad is coupled to the driver circuit. A PMOS protect circuit is coupled to the driver circuit and the pad. An NMOS protect circuit is coupled to the driver circuit and the pad. The NMOS protect circuit is configured to be activated only for a duration of the overshoot voltage received at the pad during the receive mode and the PMOS protect circuit is configured to be activated only for a duration of the undershoot voltage received at the pad during the receive mode.

Abstract: A high voltage input/output (IO) circuit designed using low voltage devices. The IO circuit receives a first bias voltage and a second bias voltage. The IO circuit includes a pre-reverse switch, a main-driver and a post-reverse switch. The pre-reverse switch includes a first capacitor and a second capacitor. The main-driver includes a first parasitic capacitance and a second parasitic capacitance. The post-reverse switch includes a third capacitor and a fourth capacitor. The first capacitor and the third capacitor counter an effect of coupling by the first parasitic capacitance on the first bias voltage and the second capacitor and the fourth capacitor counter an effect of coupling by the second parasitic capacitance on the second bias voltage.

Abstract: An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being cascaded and coupled to the node. The node is defined between the first capacitor and the second capacitor. A pad is coupled to the node. The first bias circuit maintains a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit maintains the voltage at the node below the threshold during the receive mode. The voltage at the node is dependent on a voltage at the pad during the receive mode.

Abstract: A high voltage input/output (IO) circuit designed using low voltage devices. The IO circuit receives a first bias voltage and a second bias voltage. The IO circuit includes a pre-reverse switch, a main-driver and a post-reverse switch. The pre-reverse switch includes a first capacitor and a second capacitor. The main-driver includes a first parasitic capacitance and a second parasitic capacitance. The post-reverse switch includes a third capacitor and a fourth capacitor. The first capacitor and the third capacitor counter an effect of coupling by the first parasitic capacitance on the first bias voltage and the second capacitor and the fourth capacitor counter an effect of coupling by the second parasitic capacitance on the second bias voltage.