Patents by Inventor Vinayak Gokhale

Vinayak Gokhale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hardware accelerator for convolutional neural networks and method of operation thereof
    Patent number: 11775313
    Abstract: An accelerator for processing of a convolutional neural network (CNN) includes a compute core having a plurality of compute units. Each compute unit includes a first memory cache configured to store at least one vector in a map trace, a second memory cache configured to store at least one vector in a kernel trace, and a plurality of vector multiply-accumulate units (vMACs) connected to the first and second memory caches. Each vMAC includes a plurality of multiply-accumulate units (MACs). Each MAC includes a multiplier unit configured to multiply a first word that of the at least one vector in the map trace by a second word of the at least one vector in the kernel trace to produce an intermediate product, and an adder unit that adds the intermediate product to a third word to generate a sum of the intermediate product and the third word.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 3, 2023
    Assignee: Purdue Research Foundation
    Inventors: Eugenio Culurciello, Vinayak Gokhale, Aliasger Zaidy, Andre Chang
  • Hardware Accelerator for Convolutional Neural Networks and Method of Operation Thereof
    Publication number: 20180341495
    Abstract: An accelerator for processing of a convolutional neural network (CNN) includes a compute core having a plurality of compute units. Each compute unit includes a first memory cache configured to store at least one vector in a map trace, a second memory cache configured to store at least one vector in a kernel trace, and a plurality of vector multiply-accumulate units (vMACs) connected to the first and second memory caches. Each vMAC includes a plurality of multiply-accumulate units (MACs). Each MAC includes a multiplier unit configured to multiply a first word that of the at least one vector in the map trace by a second word of the at least one vector in the kernel trace to produce an intermediate product, and an adder unit that adds the intermediate product to a third word to generate a sum of the intermediate product and the third word.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 29, 2018
    Inventors: Eugenio Culurciello, Vinayak Gokhale, Aliasger Zaidy, Andre Chang