Abstract: A method for controlling media reception at an electronic device communicating with at least one external device includes establishing a communication session between the electronic device and the at least one external device via a server; in response to establishing the communication session, creating an instance of a first reception control state machine for controlling multiple media receptions in the communication session; receiving, from the server, a media transmission notification indicating that a media reception is available from an external device; receiving, from a user of the electronic device, an input for permitting the media reception; and in response to receiving the input, transmitting a media reception request requesting the media reception to the server and creating an instance of a second reception control state machine for controlling the media reception.

Abstract: A portable communication device supporting video calls is provided. The portable communication device can be configured to perform a video call on the basis of a first video codec and a first audio codec, receive, through a touch display, a request for recording the video call, and, if the first audio codec is not supported by a designated media container, record the video call on the basis of the first video codec and a second audio codec supported by the media container.

Abstract: A circuit for modifying a clock signal, the circuit comprising: a delay unit configured to receive the clock signal and delay the clock signal so as to output a plurality of delayed versions of the clock signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a delay estimator configured to determine an amount of delay for modifying the clock signal; and a multiplexer configured to: receive each of the delayed versions of the clock signal; select a delayed version of the clock signal in dependence on the determined amount of delay; and output the selected version of the clock signal.

Abstract: A circuit for estimating a time difference between a first signal and a second signal includes a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.

Abstract: A circuit for estimating a time difference between a first signal and a second signal, the circuit comprising: a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.

Abstract: A controller for modifying a clock signal from a first clock, the controller comprising: a time comparison unit configured to estimate a time difference between a first signal associated with the first clock and a reference signal received at the controller, wherein the time comparison unit is configured to determine if the time difference is greater than or less than one clock period of the first clock; a first signal modifier configured to modify the clock signal by an integer number of clock periods; and a second signal modifier configured to modify the clock signal by a fraction of the clock period, wherein the controller is configured to select, for modifying the clock signal, the first signal modifier if the time difference is greater than one clock period or the second signal modifier if the time difference is less than one clock period.

Abstract: A controller for modifying a clock signal from a first clock, the controller comprising: a time comparison unit configured to estimate a time difference between a first signal associated with the first clock and a reference signal received at the controller, wherein the time comparison unit is configured to determine if the time difference is greater than or less than one clock period of the first clock; a first signal modifier configured to modify the clock signal by an integer number of clock periods; and a second signal modifier configured to modify the clock signal by a fraction of the clock period, wherein the controller is configured to select, for modifying the clock signal, the first signal modifier if the time difference is greater than one clock period or the second signal modifier if the time difference is less than one clock period.

Abstract: A circuit for estimating a time difference between a first signal and a second signal, the circuit comprising: a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.

Abstract: A circuit for modifying a clock signal, the circuit comprising: a delay unit configured to receive the clock signal and delay the clock signal so as to output a plurality of delayed versions of the clock signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a delay estimator configured to determine an amount of delay for modifying the clock signal; and a multiplexer configured to: receive each of the delayed versions of the clock signal; select a delayed version of the clock signal in dependence on the determined amount of delay; and output the selected version of the clock signal.