Patents by Inventor Vinayak Tilak

Vinayak Tilak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150029509
    Abstract: A device is presented. The device includes an electromagnetic guiding device to provide electromagnetic radiation, a reflector that reflects a portion of the electromagnetic radiation to generate a reflected portion of the electromagnetic radiation, wherein the reflector is fully immersed in a multiphase fluid, and a processing subsystem that analyzes the multiphase fluid based upon at least a portion of the reflected portion of the electromagnetic radiation, wherein a principal optical axis of the electromagnetic guiding device substantially aligns with a principal optical axis of the reflector.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 29, 2015
    Applicant: General Electric Company
    Inventors: Sandip Maity, Saroj Kumar Mahalik, Vinayak Tilak, Mason Harvey Guy, Neil Geoffrey Harris, Stuart John Eaton
  • Publication number: 20140262780
    Abstract: A gas sensor is disclosed. The gas sensor includes a gas sensing layer, at least one electrode, an adhesion layer, and a response modification layer adjacent to said gas sensing layer and said layer of adhesion. A system having an exhaust system and a gas sensor is also disclosed. A method of fabricating the gas sensor is also disclosed.
    Type: Application
    Filed: June 2, 2014
    Publication date: September 18, 2014
    Applicant: Amphenol Thermometries, Inc.
    Inventors: Kalaga M. KRISHNA, Geetha KARAVOOR, John P. LEMMON, Jun CUI, Vinayak TILAK, Mohandas NAYAK, Ravikumar HANUMANTHA
  • Patent number: 8765524
    Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: July 1, 2014
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
  • Patent number: 8739604
    Abstract: A gas sensor is disclosed. The gas sensor includes a gas sensing layer, at least one electrode, an adhesion layer, and a response modification layer adjacent to said gas sensing layer and said layer of adhesion. A system having an exhaust system and a gas sensor is also disclosed. A method of fabricating the gas sensor is also disclosed.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: June 3, 2014
    Assignee: Amphenol Thermometrics, Inc.
    Inventors: Kalaga Murali Krishna, Geetha Karavoor, John Patrick Lemmon, Jun Cui, Vinayak Tilak, Mohandas Nayak, Ravikumar Hanumantha
  • Patent number: 8718979
    Abstract: A high accuracy wireless sensing platform assembly comprising a sensor subassembly that is configured to obtain measurement data from a device in response to a measurand; a data transceiver assembly that is configured to communicate with an antenna assembly; a parameter coder, in communication with the sensor subassembly, that is configured to control the data transceiver assembly and/or the sensor subassembly, based on the measurement data; and a resonant circuit that is formed by the data transceiver, the sensor subassembly, and/or the parameter coder. Embodiments are capable of provide robust performance and high accuracy in harsh (e.g., hot environments). The present invention has been described in terms of specific embodiment(s), and it is recognized that equivalents, alternatives, and modifications, aside from those expressly stated, are possible and within the scope of the appending claims.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: May 6, 2014
    Assignee: General Electric Company
    Inventors: Ertugrul Berkcan, Emad Andarawis Andarawis, Vinayak Tilak
  • Patent number: 8697506
    Abstract: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: April 15, 2014
    Assignee: General Electric Company
    Inventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
  • Publication number: 20130334612
    Abstract: An integrated circuit includes a plurality of transistors. Each transistor is associated with a corresponding body terminal. At least one transistor is reverse biased at a first voltage level, and at least one other transistor is reverse biased at a second voltage level that is different from the first voltage level. Each body terminal is electrically isolated from every other body terminal via an isolation barrier. A transistor that is reverse biased at the first voltage level is electrically connected to a transistor that is reverse biased at the second voltage level, such that the electrically connected transistors operate to interact with each other while the respective body voltage levels are different from each other and are changing independently of each other during operation of the integrated circuit.
    Type: Application
    Filed: August 13, 2013
    Publication date: December 19, 2013
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Cheng-Po Chen, Emad Andarawis Andarawis, Vinayak Tilak, Zachary Matthew Stum
  • Publication number: 20130328064
    Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.
    Type: Application
    Filed: August 15, 2013
    Publication date: December 12, 2013
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
  • Patent number: 8536674
    Abstract: A method includes providing a substrate with at least one semiconducting layer. The method also includes forming a plurality of isolation barriers within the at least one semiconducting layer, thereby forming a plurality of device islands. The method further includes inserting a plurality of electronic devices into a portion of the at least one semiconducting layer such that each electronic device is substantially isolated from each other electronic device by the device islands.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 17, 2013
    Assignee: General Electric Company
    Inventors: Cheng-Po Chen, Emad Andarawis Andarawis, Vinayak Tilak, Zachary Stum
  • Patent number: 8530902
    Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: September 10, 2013
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
  • Publication number: 20130105816
    Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 2, 2013
    Inventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
  • Publication number: 20120253747
    Abstract: A high accuracy wireless sensing platform assembly comprising a sensor subassembly that is configured to obtain measurement data from a device in response to a measurand; a data transceiver assembly that is configured to communicate with an antenna assembly; a parameter coder, in communication with the sensor subassembly, that is configured to control the data transceiver assembly and/or the sensor subassembly, based on the measurement data; and a resonant circuit that is formed by the data transceiver, the sensor subassembly, and/or the parameter coder. Embodiments are capable of provide robust performance and high accuracy in harsh (e.g., hot environments). The present invention has been described in terms of specific embodiment(s), and it is recognized that equivalents, alternatives, and modifications, aside from those expressly stated, are possible and within the scope of the appending claims.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Ertugrul Berkcan, Emad Andarawis Andarawis, Vinayak Tilak
  • Publication number: 20120243182
    Abstract: A sensor assembly includes an outer housing and at least one high-impedance sensing device positioned within the outer housing. The sensor assembly also includes a buffering circuit comprising at least one wide bandgap semiconductor device positioned within the outer housing. The buffering circuit is operatively coupled to the at least one high-impedance sensing device.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Inventors: Lam Arthur Campbell, Vinayak Tilak
  • Publication number: 20120171824
    Abstract: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 5, 2012
    Inventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
  • Publication number: 20120154021
    Abstract: A method includes providing a wide bandgap semiconductor substrate that includes a first transistor and a second transistor defined thereon. The method also includes coupling the first transistor to the second transistor. The method further includes coupling a bias circuit to the first transistor and the second transistor and forming a junction therebetween. The method also includes coupling the first transistor to a first voltage source and coupling the second transistor to a second voltage source. The first voltage source and the second voltage source are configured to define a predetermined differential input voltage.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Inventors: Amita Chandrakant Patil, Vinayak Tilak, Naresh Kesavan Rao
  • Publication number: 20120155044
    Abstract: An apparatus includes a set of first metal contact pads disposed on a low temperature co-fired ceramic substrate. A plurality of metalized interconnectors extend between a digital electronic component and the low temperature co-fired ceramic substrate. The apparatus is configured to operate at a temperature greater than 250 degrees Celsius.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: David Mulford Shaddock, Vinayak Tilak, Tan Zhang
  • Publication number: 20120153427
    Abstract: A method includes providing a substrate with at least one semiconducting layer. The method also includes forming a plurality of isolation barriers within the at least one semiconducting layer, thereby forming a plurality of device islands. The method further includes inserting a plurality of electronic devices into a portion of the at least one semiconducting layer such that each electronic device is substantially isolated from each other electronic device by the device islands.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Inventors: Cheng-Po Chen, Emad Andarawis Andarawis, Vinayak Tilak, Zachary Stum
  • Patent number: 8159002
    Abstract: A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: April 17, 2012
    Assignee: General Electric Company
    Inventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
  • Patent number: 7906427
    Abstract: There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: March 15, 2011
    Assignee: General Electric Company
    Inventors: Jody Alan Fronheiser, Peter Micah Sandvik, Kevin Sean Matocha, Vinayak Tilak
  • Publication number: 20100308340
    Abstract: Provided is a device that includes a semiconductor body having a surface. Source and drain regions with effective dopant populations of a first polarity can be disposed adjacent to the surface and spaced apart from one another. A channel region with an effective dopant population of the first polarity can extend between the source and drain regions while being spaced apart from the surface. A gate region with an effective dopant population of a second polarity and first effective dopant density can extend between the source and drain regions and be disposed between the channel region and the surface. A gate contact region can be disposed between the source and drain regions and adjacent to the surface. The gate contact region can have an effective dopant population of the second polarity and a second effective dopant density greater than the first effective dopant density.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 9, 2010
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Vinayak Tilak, Peter Almern Losee