Patents by Inventor Vinaykumar V. HADAGALI

Vinaykumar V. HADAGALI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HYBRID ETCH STOP LAYERS
    Publication number: 20230317615
    Abstract: An integrated circuit includes a first layer, and a second layer above the first layer. A third layer is between a first section of the first layer and a first section of the second layer. A fourth layer is laterally adjacent to the third layer, the fourth layer between a second section of the first layer and a second section of the second layer. In an example, a first dielectric material of the third layer is different (e.g., one or both of compositionally different and structurally different) from a second dielectric material of the fourth layer. In an example, the third and fourth layers are etch stop layers. In some cases, the third and fourth layers are coplanar with each other with respect to their top surfaces, or their bottom surfaces, or both their top and bottom surfaces.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Deepyanti Taneja, Travis W. Lajoie, Abhishek Anil Sharma, Gregory J. George, Tarannum Tiasha, Huiying Liu, Yue Liu, Moshe Dolejsi, Vinaykumar V. Hadagali, Shardul Wadekar, Vladimir Nikitin, Albert B. Chen, Daniel J. Schinke, James O'Donnell
  • Intermediate separation layers at the back-end-of-line
    Patent number: 11652047
    Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Ting Chen, Vinaykumar V. Hadagali
  • INTERMEDIATE SEPARATION LAYERS AT THE BACK-END-OF-LINE
    Publication number: 20200411426
    Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Julie ROLLINS, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Ting CHEN, Vinaykumar V. HADAGALI