Abstract: This disclosure provides systems, methods and apparatus for providing an output voltage to be used in a display device. In one aspect, a circuit may include switches and a digital-to-analog converter (DAC). A charge recycling circuit may include a capacitive voltage divider providing voltage supplies for the switches to select from and provide to the DAC. A storage capacitor may be configured to be coupled one at a time and in parallel with individual capacitors of the capacitive voltage divider. The storage capacitor may store charge that may be reused. Additionally, a data control circuit may provide control signals for the switches and the DAC.

Abstract: This disclosure provides systems, methods and apparatus for recycling charge. In one aspect, a circuit may include amplifiers with power supplies provided by a capacitor voltage divider. A storage capacitor may be configured to be coupled one at a time and in parallel with individual capacitors of the voltage divider. The storage capacitor may store charge that may be reused.

Abstract: A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: An electronic product includes an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product. The capless regulator module includes both a low-power sub-module and a high-power sub-module. Control logic of the ASIC is configured to determine if an external capacitance is present. If so, the control logic causes the high-power capless regulator sub-module to be used during a power-up phase of the ASIC; if not, only the low-power capless regulator sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: In an integrated circuit, capacitively coupled interference (digital-switching or analog cross-talk) is prevented by constructing shielded coaxial conductors for the analog signals. The coaxial configuration comprises a primary conductor for the analog signal surrounded by a secondary conductor that is electrically isolated from the primary one and that is connected to a clean power bus such as GND or Vdd. The outer secondary conductor shunts the digital noise energy to the power bus, preventing it from injecting noise into the analog primary conductor. A similar coaxial configuration is provided with a bootstrap follower to reduce the effects of parasitic capacitance for high-speed and small analog signals.