Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

Abstract: The invention relates to methods of interleaving payload data and integrity control data in an external memory interfaced with a microcontroller to improve data integrity check, enhance data confidentiality and save internal memory. Data words are received for storing in the external memory. Each data word is used to generate a respective integrity word, while an associated logic address is translated to two physical addresses in the external memory, one for the data word and the other for the integrity word. The two physical addresses for the data and integrity words are interleaved in the external memory, and sometimes, in a periodic scheme. In particular, each data word may be associated to an integrity sub-word included in an integrity word having the same length with that of a data word. The external memory may have dedicated regions for the data words and the integrity words, respectively.

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

Abstract: Initiating data transactions on a system bus is disclosed. In some implementations, a controller receives first information from a first peripheral requesting a first data transaction. The first information is received over a first communication link between the controller and the first peripheral. The controller receives second information from a second peripheral requesting a second data transaction. The second information received over a second communication link between the controller and the second peripheral. The controller determines first and second ranks for the first and second data transactions, respectively, based on the first and second information, and initiates based on the first and second ranks, the first and second data transactions on a system bus.

Abstract: The disclosure describes a display controller and a method that includes monitoring a fill-level of a first in, first out (FIFO) block in the display controller, generating a regulation signal that depends on the fill-level of the FIFO block, and regulating, based on the regulation signal, access to a system interconnect by a master unit other than the display controller.

Abstract: A controller coupled to a peripheral identifies an access type used by the controller for data transfer. The controller performs operations including: sending information to a peripheral coupled to a controller, the information indicating an access type for which the controller is configured for data transfer; monitoring a communication link with the peripheral for a signal indicating that the peripheral is ready to perform a data transfer according to the access type; and performing, in response to a receipt of the signal through the communication link, the data transfer using data transfer handshake signals that are adapted according to the access type.

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

Abstract: A microcontroller system is disclosed that includes an access stealing monitor coupled to a bus that is configured to receive a first access request from the bus for a first peripheral, duplicate the first access request, transform the first access request to a second access request on a second peripheral, and transfer the second access request to the bus. In another embodiment, a first peripheral coupled to the bus is configured to receive a first access request from the bus for the first peripheral, duplicate the first access request and transform the first access request to a second access request. A second peripheral coupled to the bus and to the first peripheral is configured to receive the second access request and to respond to the second access request. Methods of access stealing in a microcontroller system are also disclosed.

Abstract: A microcontroller system is disclosed that includes an access stealing monitor coupled to a bus that is configured to receive a first access request from the bus for a first peripheral, duplicate the first access request, transform the first access request to a second access request on a second peripheral, and transfer the second access request to the bus. In another embodiment, a first peripheral coupled to the bus is configured to receive a first access request from the bus for the first peripheral, duplicate the first access request and transform the first access request to a second access request. A second peripheral coupled to the bus and to the first peripheral is configured to receive the second access request and to respond to the second access request. Methods of access stealing in a microcontroller system are also disclosed.

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract: The present invention relates to key management in a secure microcontroller, and more particularly, to systems, devices and methods of automatically and transparently employing logic or physical address based keys that may also be transferred using dedicated buses. A cryptographic engine translates a logic address to at least one physical address, and processes a corresponding data word based on at least one target key. The target key is selected from a plurality of keys based on the logic or physical address. A universal memory controller stores each processed data word in the corresponding physical address within a memory. Each key is associated with a memory region within the memory, and therefore, the logic or physical address associated with a memory region may be used to automatically identify the corresponding target key. A dedicated secure link may be used to transport key request commands and the plurality of keys.

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract: A controller coupled to a peripheral identifies an access type used by the controller for data transfer. The controller performs operations including: sending information to a peripheral coupled to a controller, the information indicating an access type for which the controller is configured for data transfer; monitoring a communication link with the peripheral for a signal indicating that the peripheral is ready to perform a data transfer according to the access type; and performing, in response to a receipt of the signal through the communication link, the data transfer using data transfer handshake signals that are adapted according to the access type.

Abstract: Initiating data transactions on a system bus is disclosed. In some implementations, a controller receives first information from a first peripheral requesting a first data transaction. The first information is received over a first communication link between the controller and the first peripheral. The controller receives second information from a second peripheral requesting a second data transaction. The second information received over a second communication link between the controller and the second peripheral. The controller determines first and second ranks for the first and second data transactions, respectively, based on the first and second information, and initiates based on the first and second ranks, the first and second data transactions on a system bus.

Abstract: The present invention relates to key management in a secure microcontroller, and more particularly, to systems, devices and methods of automatically and transparently employing logic or physical address based keys that may also be transferred using dedicated buses. A cryptographic engine translates a logic address to at least one physical address, and processes a corresponding data word based on at least one target key. The target key is selected from a plurality of keys based on the logic or physical address. A universal memory controller stores each processed data word in the corresponding physical address within a memory. Each key is associated with a memory region within the memory, and therefore, the logic or physical address associated with a memory region may be used to automatically identify the corresponding target key. A dedicated secure link may be used to transport key request commands and the plurality of keys.

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract: The present invention relates to key management in a secure microcontroller, and more particularly, to systems, devices and methods of automatically and transparently employing logic or physical address based keys that may also be transferred using dedicated buses. A cryptographic engine translates a logic address to at least one physical address, and processes a corresponding data word based on at least one target key. The target key is selected from a plurality of keys based on the logic or physical address. A universal memory controller stores each processed data word in the corresponding physical address within a memory. Each key is associated with a memory region within the memory, and therefore, the logic or physical address associated with a memory region may be used to automatically identify the corresponding target key. A dedicated secure link may be used to transport key request commands and the plurality of keys.