Abstract: A semiconductor storage device 1 includes: an input controller (3); and a content-addressable memory block (2) connected to the input controller (3). Each word circuit (4) of the content-addressable memory block (2) includes: a k-bit 1st-stage sub word (4a) connected to search line 1 (SL1) of the input controller (3); and an (n-k)-bit 2nd-stage sub word (4b) connected to search line 2 (SL2) of the input controller (3). The k-bit 1st-stage sub word (4a) and the (n-k)-bit 2nd-stage sub word (4b) are separated by a segmentation circuit (5). When the 1st-stage sub word outputs a match signal, the match result is stored in the segmentation circuit (5), and a plurality of local match circuits within the 2nd-stage sub word (4b) are operated.

Abstract: A semiconductor storage device 1 includes: an input controller (3); and a content-addressable memory block (2) connected to the input controller (3). Each word circuit (4) of the content-addressable memory block (2) includes: a k-bit 1st-stage sub word (4a) connected to search line 1 (SL1) of the input controller (3); and an (n-k)-bit 2nd-stage sub word (4b) connected to search line 2 (SL2) of the input controller (3). The k-bit 1st-stage sub word (4a) and the (n-k)-bit 2nd-stage sub word (4b) are separated by a segmentation circuit (5). When the 1st-stage sub word outputs a match signal, the match result is stored in the segmentation circuit (5), and a plurality of local match circuits within the 2nd-stage sub word (4b) are operated.

Abstract: Decoder for low-density parity check convolutional codes. In at least some embodiments, a decoder (200) for arbitrary length blocks of low-density, parity-check codes includes a plurality of interconnected processors (202), which further include a plurality of interconnected nodes. A memory can be interconnected with the nodes to store intermediate log likelihood ratio (LLR) values based on channel LLR values. Thus, LLR values having successively improved accuracy relative to the channel LLR values can be output from each processor, and eventually used to decision information bits. In some embodiments, the memory is a random access memory (RAM) device that is adapted to store the intermediate LLR values in a circular buffer. Additionally, a storage device such as a read-only memory (ROM) device can be used to generate a predetermined plurality of addresses for reading and writing LLR values.

Abstract: An architecture and a method are provided for decoding codewords for codes such as low density parity check (LDPC) codes. An iterative decoding algorithm such as the Belief Propagation Algorithm (BPA) is employed that attempts to correct errors in an input block of symbols via a structure containing two sets of nodes through node processing and the passing of messages between nodes. Message passing and node processing is performed in a digit-serial manner instead of a bit-parallel manner.

Abstract: An architecture and a method are provided for decoding codewords for codes such as low density parity check (LDPC) codes. An iterative decoding algorithm such as the Belief Propagation Algorithm (BPA) is employed that attempts to correct errors in an input block of symbols via a structure containing two sets of nodes through node processing and the passing of messages between nodes. Message passing and node processing is performed in a digit-serial manner instead of a bit-parallel manner.

Abstract: Decoder for low-density parity check convolutional codes. In at least some embodiments, a decoder (200) for arbitrary length blocks of low-density, parity-check codes includes a plurality of interconnected processors (202), which further include a plurality of interconnected nodes. A memory can be interconnected with the nodes to store intermediate log likelihood ratio (LLR) values based on channel LLR values. Thus, LLR values having successively improved accuracy relative to the channel LLR values can be output from each processor, and eventually used to decision information bits. In some embodiments, the memory is a random access memory (RAM) device that is adapted to store the intermediate LLR values in a circular buffer. Additionally, a storage device such as a read-only memory (ROM) device can be used to generate a predetermined plurality of addresses for reading and writing LLR values.