Abstract: An emulation system (1) comprises a programming system (2) made up of a laptop computer (2(a)) and a central server (2(b)), an interrogation station (3), and a programmable storage peripheral device (4). The system (1) links with an existing disk storage peripheral device (10) to retrieve characterisation data, and upload it to the central server (2(b)). The laptop computer (2(a)) then retrieves the characterization data and then programs the programmable device (4) to emulate the full functionality of the pre-existing computer storage peripheral (10). The device (4) is programmed by the host computer (2) to fully replicate characteristics including electrical and timing characteristics and command responses. The programmable device (4) does not have a disk drive, the only storage components being solid state non-volatile memory components, in this embodiment flash memory and volatile components including DRAM. The flash components include mostly NAND flash, but also NOR flash.

Abstract: A method and system for optimizing use of signal paths on a DRAM interface. Signal paths that have a ‘don't care’ status during DRAM refresh are assigned to communication with another device. Onset of the refresh procedure triggers diversion of shared signal paths away from the DRAM to the other device for the duration of the refresh the shared signal paths include at least some of the address and data signal paths.

Abstract: A network switch which allows a network processor to process resultant data from a look-up engine while the look-up engine proceeds to deal with a subsequent packet. The look-up engine stores the resultant data in registers from which the resultant data is written back for the packet if the processor does not intervene. If the processor intervenes it acts on the resultant data, which is written back for the packet only after the processor has finished. A system of pointers and busy bits ensures that the packet is not forwarded until the look-up engine and (if required) the network processor have completed their operations in relation to the packet.

Abstract: A unit for receiving and re-transmitting data signals comprising multi-byte packets separated by multi-byte inter-packet gaps includes a FIFO store, a first, write, state machine for controlling the writing of packets into the FIFO and a second, read, state machine for controlling read-out of packets from the FIFO. The first state machine is controlled by a recovered clock and the second state machine is controlled by a local system clock. The first state machine is operative in a writing sequence to write into the FIFO the words of each received packet in successive locations and thereafter to cause the writing into the FIFO of a succession of idle bytes representing a selected inter-packet gap; and the second state machine is operative in response to maintain a reading sequence in arrears of the writing sequence by a selected number of said locations. The arrangement maintains the inter-packet gap despite slight differences between the recovered clock and the system clock.

Abstract: A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.

Abstract: A stackable network unit which can form a ring with other units has a master mode in which it can place packets on the ring, so that they can be ultimately forwarded from other units, and a repeat mode in which it can make a request for transfer of mastership of the ring, inserting bits in a header of an arbitration packet. If a master unit has completed the transmission of a packet and, preferably, after the required inter-packet gap has elapsed, it has not yet received an arbitration header to permit the making of an arbitration decision it can transmit a subsequent packet. The header information of this packet indicates to the other units that this subsequent packet is part of a burst of packets and the other units should not set requests in the header of this packet because this packet would not be used for arbitration.

Abstract: An application specific integrated circuit includes a multiplicity of operational blocks each of which includes at least one respective data bus and at least one respective visibility bus and a respective addressable multiplexer for selecting between those buses to provide an output on a to respective block bus. An interface block includes a first addressable multiplexer for selecting output data from a selected one of the blocks and providing an output; a register coupled to the output of the first addressable multiplexer; and a second addressable multiplexer for selecting between data provided by the output of the first addressable multiplexer and data in the register. Different portions of externally supplied address words are applied to the first addressable multiplexer and the respective addressable multiplexer, and a decoder is responsive to the address words for controlling the second addressable multiplexer. The arrangement provides a common multiplexing system for data buses and visibility buses.

Abstract: A network switch which allows a network processor to process resultant data from a look-up engine while the look-up engine proceeds to deal with a subsequent packet. The look-up engine stores the resultant data in registers from which the resultant data is written back for the packet if the processor does not intervene. If the processor intervenes it acts on the resultant data, which is written back for the packet only after the processor has finished. A system of pointers and busy bits ensures that the packet is not forwarded until the look-up engine and (if required) the network processor have completed their operations in relation to the packet.

Abstract: A method and system for optimizing use of signal paths on a DRAM interface. Signal paths that have a ‘don't care’ status during DRAM refresh are assigned to communication with another device. Onset of the refresh procedure triggers diversion of shared signal paths away from the DRAM to the other device for the duration of the refresh. the shared signal paths include at least some of the address and data signal paths.

Abstract: A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.

Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths

Abstract: A data bus system in which a read or write transaction includes an identification of the initiator of the transaction and optionally an identification of the transaction as a number in a cyclic progression and optionally a request for an acknowledgement.

Abstract: An application specific integrated circuit includes a multiplicity of operative circuit blocks. Disposed in at least one of the blocks is a multiplicity of selectively operative heater modules for providing localised heating within the block. The heater modules may comprise cyclic redundancy code generators each coupled to respond to a system clock, and each heater module may include a system clock divider providing a multiplicity of differently divided clock signals and means for selecting a clock signal for use by the module. The invention is useful in design variable testing to produce variation with temperature of the frequency of an intermittent timing error.

Abstract: A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronisers

Abstract: A communication system comprises a plurality of interfaces disposed for sending data packets by way of virtual circuit connections and for receiving data packets by way of virtual circuit connections in an asynchronous transfer mode. The interfaces by means of the virtual circuit connections emulate at least one local area network including unit for establishing a virtual circuit connection functioning as a BUS (broadcast and unknown server) for the broadcast of data packets throughout the emulated local area network. An asynchronous transfer mode switch receives packets by way of virtual circuit connections from each of said the interfaces, replicates the packets and sends them to all the other interfaces, thus to establish a mesh between said interfaces. At least one interface comprises a unit for mapping virtual circuit connections between one interface and at least one terminal which is not directly connectable in the mesh connection into virtual circuit connections in the mesh.

Abstract: Data received in the form of data packets which include destination addresses is transmitted over virtual channels in an asynchronous transfer mode to emulate the operation of a plurality of emulated local area networks. A plurality of bus channels are provided, each specified for the broadcast transmission of data packets to members of a respective one of the emulated local area networks. An address look-up data-base is used to receive the destination address of a data packet and data defining the respective bus channel for the broadcast transmission of that packet in the respective emulated local area network. The data packet is then transmitted over the respective bus channel. The content addressable memory provides a data field which indicates whether a request for the resolution of the destination address into a specific virtual channel number has been made.

Abstract: Apparatus for monitoring and controlling data flow ina computer network device having a plurality of parts comprises control means for directly linking ports together on the basis of additional information stored in the control means whereby incoming packets are linked directly to an utput port to achieve high performance. The additional information is stored in one more look-up tables additional to the normal CAm with the or each table addressed by separate processing. This allows the implementation to be in hardware rather than in software.