Abstract: An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In an exemplary embodiment, the antifuse cell uses only a single external access pin. Once the antifuse device is blown and during subsequent power-up operations, intrusion is prevented.

Abstract: An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In an exemplary embodiment, the antifuse cell uses only a single external access pin. Once the antifuse device is blown and during subsequent power-up operations, intrusion is prevented.

Abstract: An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In an exemplary embodiment, the antifuse cell uses only a single external access pin. Once the antifuse device is blown and during subsequent power-up operations, intrusion is prevented.

Abstract: An antifuse programming, protection, and sensing device incorporates a control circuit to program and protect an antifuse. The antifuse, which is initially constructed as a low conductivity path, is programmable to a high conductivity path by application of an elevated voltage across terminals of the antifuse. Application of 0 volts to the VDD node of a conduction control portion of the antifuse programming, protection, and sensing device allows an elevated voltage for programming to be applied to the antifuse. Upon application of a nominal working voltage to the VDD node of the conduction control circuitry, the antifuse and an adjoining sense amplifier circuit are protected from overvoltage and tampering. The sense amplifier supplies a sense current to the antifuse, measures a voltage at an input to the antifuse, and determines a programmed state if a measured voltage level is low.

Abstract: An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In an exemplary embodiment, the antifuse cell uses only a single external access pin. Once the antifuse device is blown and during subsequent power-up operations, intrusion is prevented.

Abstract: An antifuse programming, protection, and sensing device incorporates a control circuit to program and protect an antifuse. The antifuse, which is initially constructed as a low conductivity path, is programmable to a high conductivity path by application of an elevated voltage across terminals of the antifuse. Application of 0 volts to the VDD node of a conduction control portion of the antifuse programming, protection, and sensing device allows an elevated voltage for programming to be applied to the antifuse. Upon application of a nominal working voltage to the VDD node of the conduction control circuitry, the antifuse and an adjoining sense amplifier circuit are protected from overvoltage and tampering. The sense amplifier supplies a sense current to the antifuse, measures a voltage at an input to the antifuse, and determines a programmed state if a measured voltage level is low.

Abstract: An input/output (I/O) buffer having an input mode and coupled between first and second supply voltages includes a PMOS pull-up transistor fabricated in an nwell, and a gate bias control transistor coupled to the gate of the PMOS pull-up transistor for coupling the gate of the PMOS pull-up transistor to an input/output node in response to an input signal having a voltage greater than approximately the first supply voltage. A well bias control circuit is coupled to the PMOS pull-up transistor and to a well drive transistor to couple the nwell terminal to the first supply voltage in response to the input signal having a voltage approximately equal to or less than the first supply voltage.

Abstract: An input/output (I/O) buffer having an input mode and coupled between first and second supply voltages includes a PMOS pull-up transistor fabricated in an nwell, and a gate bias control transistor coupled to the gate of the PMOS pull-up transistor for coupling the gate of the PMOS pull-up transistor to an input/output node in response to an input signal having a voltage greater than approximately the first supply voltage. A well bias control circuit is coupled to the PMOS pull-up transistor and to a well drive transistor to couple the nwell terminal to the first supply voltage in response to the input signal having a voltage approximately equal to or less than the first supply voltage.