Patents by Inventor Vincent M. Donnelly
Vincent M. Donnelly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10515782Abstract: A system and method for rapid atomic layer etching (ALET) including a pulsed plasma source, with a spiral coil electrode, a cooled Faraday shield, a counter electrode disposed at the top of the tube, a gas inlet and a reaction chamber including a substrate support and a boundary electrode. The method includes positioning an etchable substrate in a plasma etching chamber, forming a product layer on the surface of the substrate, removing a portion of the product layer by pulsing a plasma source, then repeating the steps of forming a product layer and removing a portion of the product layer to form an etched substrate.Type: GrantFiled: April 10, 2018Date of Patent: December 24, 2019Assignee: UNIVERSITY OF HOUSTON SYSTEMInventors: Vincent M. Donnelly, Demetre J. Economou
-
Patent number: 10207469Abstract: Nanopantography is a method for patterning nanofeatures over large areas. Transfer of patterns defined by nanopantography using highly selective plasma etching, with an oxide layer of silicon serving as a hard mask, can improve patterning speed and etch profile. With this method, high aspect ratio features can be fabricated in a substrate with no mask undercut. The ability to fabricate complex patterns using nanopantography, followed by highly selective plasma etching, provides improved patterning speed, feature aspect ratio, and etching profile.Type: GrantFiled: December 8, 2015Date of Patent: February 19, 2019Assignee: UNIVERSITY OF HOUSTON SYSTEMInventors: Vincent M. Donnelly, Demetre J. Economou, Siyuan Tian
-
Publication number: 20180226227Abstract: A system and method for rapid atomic layer etching (ALET) including a pulsed plasma source, with a spiral coil electrode, a cooled Faraday shield, a counter electrode disposed at the top of the tube, a gas inlet and a reaction chamber including a substrate support and a boundary electrode. The method includes positioning an etchable substrate in a plasma etching chamber, forming a product layer on the surface of the substrate, removing a portion of the product layer by pulsing a plasma source, then repeating the steps of forming a product layer and removing a portion of the product layer to form an etched substrate.Type: ApplicationFiled: April 10, 2018Publication date: August 9, 2018Applicant: University of Houston SystemInventors: Vincent M. Donnelly, Demetre J. Economou
-
Publication number: 20170361551Abstract: Nanopantography is a method for patterning nanofeatures over large areas. Transfer of patterns defined by nanopantography using highly selective plasma etching, with an oxide layer of silicon serving as a hard mask, can improve patterning speed and etch profile. With this method, high aspect ratio features can be fabricated in a substrate with no mask undercut. The ability to fabricate complex patterns using nanopantography, followed by highly selective plasma etching, provides improved patterning speed, feature aspect ratio, and etching profile.Type: ApplicationFiled: December 8, 2015Publication date: December 21, 2017Inventors: Vincent M. Donnelly, Demetre J. Economou, Siyuan Tian
-
Patent number: 8968588Abstract: A surface wave plasma (SWP) source couples pulsed microwave (MW) energy into a processing chamber through, for example, a radial line slot antenna, to result in a low mean electron energy (Te). To prevent impingement of the microwave energy onto the surface of a substrate when plasma density is low between pulses, an ICP source, such as a helical inductive source, a planar RF coil, or other inductively coupled source, is provided between the SWP source and the substrate to produce plasma that is opaque to microwave energy. The ICP source can also be pulsed in synchronism with the pulsing of the MW plasma in phase with the ramping up of the MW pulses. The ICP also adds an edge dense distribution of plasma to a generally chamber centric MW plasma to improve plasma uniformity.Type: GrantFiled: March 30, 2012Date of Patent: March 3, 2015Assignee: Tokyo Electron LimitedInventors: Jianping Zhao, Lee Chen, Vincent M. Donnelly, Demetre J. Economou, Merritt Funk, Radha Sundararajan
-
Publication number: 20130256272Abstract: A surface wave plasma (SWP) source couples pulsed microwave (MW) energy into a processing chamber through, for example, a radial line slot antenna, to result in a low mean electron energy (Te). To prevent impingement of the microwave energy onto the surface of a substrate when plasma density is low between pulses, an ICP source, such as a helical inductive source, a planar RF coil, or other inductively coupled source, is provided between the SWP source and the substrate to produce plasma that is opaque to microwave energy. The ICP source can also be pulsed in synchronism with the pulsing of the MW plasma in phase with the ramping up of the MW pulses. The ICP also adds an edge dense distribution of plasma to a generally chamber centric MW plasma to improve plasma uniformity.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Jianping Zhao, Lee Chen, Vincent M. Donnelly, Demetre J. Economou, Merritt Funk, Radha Sundararajan
-
Patent number: 8030620Abstract: A method is provided for creating a plurality of substantially uniform nano-scale features in a substantially parallel manner in which an array of micro-lenses is positioned on a surface of a substrate, where each micro-lens includes a hole such that the bottom of the hole corresponds to a portion of the surface of the substrate. A flux of charged particles, e.g., a beam of positive ions of a selected element, is applied to the micro-lens array. The flux of charged particles is focused at selected focal points on the substrate surface at the bottoms of the holes of the micro-lens array. The substrate is tilted at one or more selected angles to displace the locations of the focal points across the substrate surface. By depositing material or etching the surface of the substrate, several substantially uniform nanometer sized features may be rapidly created in each hole on the surface of the substrate in a substantially parallel manner.Type: GrantFiled: May 5, 2009Date of Patent: October 4, 2011Assignee: University of HoustonInventors: Vincent M. Donnelly, Demetre J. Economou, Paul Ruchhoeft, Lin Xu, Sri Charan Vemula, Manish Kumar Jain
-
Publication number: 20110139748Abstract: A system and method for rapid atomic layer etching (ALET) including a pulsed plasma source, with a spiral coil electrode, a cooled Faraday shield, a counter electrode disposed at the top of the tube, a gas inlet and a reaction chamber including a substrate support and a boundary electrode. The method includes positioning an etchable substrate in a plasma etching chamber, forming a product layer on the surface of the substrate, removing a portion of the product layer by pulsing a plasma source, then repeating the steps of forming a product layer and removing a portion of the product layer to form an etched substrate.Type: ApplicationFiled: December 13, 2010Publication date: June 16, 2011Applicant: UNIVERSITY OF HOUSTONInventors: Vincent M. DONNELLY, Demetre J. ECONOMOU
-
Patent number: 7883839Abstract: A method is provided for creating a plurality of substantially uniform nano-scale features in a substantially parallel manner in which an array of micro-lenses is positioned on a surface of a substrate, where each micro-lens includes a hole such that the bottom of the hole corresponds to a portion of the surface of the substrate. A flux of charged particles, e.g., a beam of positive ions of a selected element, is applied to the micro-lens array. The flux of charged particles is focused at selected focal points on the substrate surface at the bottoms of the holes of the micro-lens array. The substrate is tilted at one or more selected angles to displace the locations of the focal points across the substrate surface. By depositing material or etching the surface of the substrate, several substantially uniform nanometer sized features may be rapidly created in each hole on the surface of the substrate in a substantially parallel manner.Type: GrantFiled: December 4, 2006Date of Patent: February 8, 2011Assignee: University of HoustonInventors: Vincent M Donnelly, Demetre J. Economou, Paul Ruchhoeft, Lin Xu, Sri Charan Vemula, Manish Kumar Jain
-
Patent number: 7638759Abstract: Method and system for pumping a hyperthermal neutral beam source is described. The pumping system enables use of the hyperthermal neutral beam source for semiconductor processing applications, such as etching processes. An embodiment is described having a neutral beam source coupled to a processing chamber through a neutralizing grid. Control is provided by separately pumping the neutral beam source and the processing chamber.Type: GrantFiled: February 18, 2008Date of Patent: December 29, 2009Assignee: Tokyo Electron LimitedInventors: Demetre J. Economou, Lee Chen, Vincent M. Donnelly
-
Publication number: 20090283215Abstract: A method is provided for creating a plurality of substantially uniform nano-scale features in a substantially parallel manner in which an array of micro-lenses is positioned on a surface of a substrate, where each micro-lens includes a hole such that the bottom of the hole corresponds to a portion of the surface of the substrate. A flux of charged particles, e.g., a beam of positive ions of a selected element, is applied to the micro-lens array. The flux of charged particles is focused at selected focal points on the substrate surface at the bottoms of the holes of the micro-lens array. The substrate is tilted at one or more selected angles to displace the locations of the focal points across the substrate surface. By depositing material or etching the surface of the substrate, several substantially uniform nanometer sized features may be rapidly created in each hole on the surface of the substrate in a substantially parallel manner.Type: ApplicationFiled: May 5, 2009Publication date: November 19, 2009Applicant: University of HoustonInventors: Vincent M. Donnelly, Demetre J. Economou, Paul Ruchhoeft, Lin Xu, Sri Charan Vemula, Manish Kumar Jain
-
Publication number: 20080135742Abstract: Method and system for pumping a hyperthermal neutral beam source is described. The pumping system enables use of the hyperthermal neutral beam source for semiconductor processing applications, such as etching processes. An embodiment is described having a neutral beam source coupled to a processing chamber through a neutralizing grid. Control is provided by separately pumping the neutral beam source and the processing chamber.Type: ApplicationFiled: February 18, 2008Publication date: June 12, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Demetre J. Economou, Lee Chen, Vincent M. Donnelly
-
Patent number: 7358484Abstract: Method and system for pumping a hyperthermal neutral beam source is described. The pumping system enables use of the hyperthermal neutral beam source for semiconductor processing applications, such as etching processes. An embodiment is described having a neutral beam source coupled to a processing chamber through a neutralizing grid. Control is provided by separately pumping the neutral beam source and the processing chamber.Type: GrantFiled: September 29, 2005Date of Patent: April 15, 2008Assignee: Tokyo Electron LimitedInventors: Demetre J. Economou, Lee Chen, Vincent M. Donnelly
-
Patent number: 6511872Abstract: The present invention provides a method of manufacturing a semiconductor device. The method includes depositing a metal oxide containing a dopant and having a high dielectric constant on a substrate; wherein the metal is aluminum or silicon and the dopant is zirconium or hafnium and etching the doped metal oxide with a plasma containing a halogenated compound.Type: GrantFiled: July 10, 2001Date of Patent: January 28, 2003Assignee: Agere Systems Inc.Inventors: Vincent M. Donnelly, Jr., Avinoam Kornblit, Kalman Pelhos
-
Publication number: 20030013269Abstract: The present invention provides a method of manufacturing a semiconductor device. The method includes depositing a metal oxide containing a dopant and having a high dielectric constant on a substrate; wherein the metal is aluminum or silicon and the dopant is zirconium or hafnium and etching the doped metal oxide with a plasma containing a halogenated compound.Type: ApplicationFiled: July 10, 2001Publication date: January 16, 2003Inventors: Vincent M. Donnelly, Avinoam Kornblit, Kalman Pelhos
-
Patent number: 5467732Abstract: A method for fabricating a semiconductor device, which involves a technique for monitoring the temperature of the semiconductor substrate in which the device is formed, is disclosed. In accordance with the inventive technique, light, to which the substrate is substantially transparent, is impinged upon the substrate, and the intensity of either the reflected or transmitted light is monitored. If, for example, the intensity of the reflected light is monitored, then this intensity will be due to an interference between the light reflected from the upper surface of the semiconductor substrate and the light transmitted through the substrate and reflected upwardly from the lower surface of the substrate. If the temperature of the substrate varies, then the optical path length of the light within the substrate will vary, resulting in a change in the detected intensity.Type: GrantFiled: May 21, 1993Date of Patent: November 21, 1995Assignee: AT&T Corp.Inventors: Vincent M. Donnelly, Jr., James A. McCaulley
-
Patent number: 5229303Abstract: A method for fabricating a semiconductor device, which involves a technique for monitoring the temperature of the semiconductor substrate in which the device is formed, is disclosed. In accordance with the inventive technique, light, to which the substrate is substantially transparent, is impinged upon the substrate, and the intensity of either the reflected or transmitted light is monitored. If, for example, the intensity of the reflected light is monitored, then this intensity will be due to an interference between the light reflected from the upper surface of the semiconductor substrate and the light transmitted through the substrate and reflected upwardly from the lower surface of the substrate. If the temperature of the substrate varies, then the optical path length of the light within the substrate will vary, resulting in a change in the detected intensity.Type: GrantFiled: December 13, 1991Date of Patent: July 20, 1993Assignee: AT&T Bell LaboratoriesInventors: Vincent M. Donnelly, Jr., James A. McCaulley
-
Patent number: 4645687Abstract: A low temperature procedure for depositing III-V semiconductor materials that offers the possibility of higher deposition rates together with abrupt junction formation has been found. This process involves the irradiation at a deposition substrate with a high power density radiation source of deposition gases such as organometallic materials, e.g., trimethyl gallium and trimethyl indium. By utilizing a sufficiently high power density, multiphoton processes are induced in the deposition gas that, in turn, lead to advantageous deposited materials.Type: GrantFiled: September 16, 1985Date of Patent: February 24, 1987Assignee: AT&T LaboratoriesInventors: Vincent M. Donnelly, Robert F. Karlicek, Jr.
-
Patent number: 4498953Abstract: A highly selective--greater than 100 to 1--etch for silicon, tantalum, tantalum silicide and tantalum nitride is achieved by using polyatomic halogen fluorides. The selectivity is achievable without employing plasmas or wet etching.Type: GrantFiled: July 27, 1983Date of Patent: February 12, 1985Assignee: AT&T Bell LaboratoriesInventors: Joel M. Cook, Vincent M. Donnelly, Daniel L. Flamm, Dale E. Ibbotson, John A. Mucha
-
Patent number: 4397711Abstract: Crystallographic etching in III-V semiconductor materials such as GaAs is achieved, for example, by utilizing a suitable halogen containing entity such as chlorine, bromine and iodine. This crystallographic etching yields in one embodiment essentially vertical surfaces of optical quality. Therefore, the procedure is useful in fabricating integrated circuits and in producing optical devices.Type: GrantFiled: October 1, 1982Date of Patent: August 9, 1983Assignee: Bell Telephone Laboratories, IncorporatedInventors: Vincent M. Donnelly, Daniel L. Flamm, Dale E. Ibbotson