Abstract: A video transceiver includes a compressor which grabs a pair of blocks of image data from a video frame store and loads them into a dual port memory. A first processor, working through one of the dual ports, performs a portion of an image compression algorithm, while a second processor, working through a second one of the dual ports, performs the remainder of the compression algorithm on each one of the two pairs of blocks, both processors operating in parallel to speed up the entire process. A key word in each block is changed in accordance with each step, so that each of the two processors is prevented from grabbing the wrong one of the two blocks from the dual port memory. The resulting compressed data is queued in a temporary buffer, from which it is returned to another portion of the video frame store in serial fashion, rather than block, in preparation for serial transmission.