Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors such that at least one input vector of the plurality of input vectors is transmitted to the memory macro in each of a plurality of cycles, receiving in each of the plurality of cycles, an output data from the memory macro. The output data is generated by the memory macro in response to processing the at least one input vector. The BIST also includes comparing the output data in each of the plurality of cycles with a signature value and determining whether the memory macro is normal or faulty based upon the comparison.

Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors such that at least one input vector of the plurality of input vectors is transmitted to the memory macro in each of a plurality of cycles, receiving in each of the plurality of cycles, an output data from the memory macro. The output data is generated by the memory macro in response to processing the at least one input vector. The BIST also includes comparing the output data in each of the plurality of cycles with a signature value and determining whether the memory macro is normal or faulty based upon the comparison.

Abstract: Disclosed herein is a method. The method is implemented by an authentication engine stored on a memory as processor executable instructions. The processor executable instructions are executed by at least one processor. The method (i.e., as implemented by the authentication engine) includes determining an authentication mechanism for an external system to a software platform, generating an interface, executing the authentication mechanism within the interface, authenticating an entity within the interface, and provisioning element instance details with respect to the authentication of the entity.

Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors such that at least one input vector of the plurality of input vectors is transmitted to the memory macro in each of a plurality of cycles, receiving in each of the plurality of cycles, an output data from the memory macro. The output data is generated by the memory macro in response to processing the at least one input vector. The BIST also includes comparing the output data in each of the plurality of cycles with a signature value and determining whether the memory macro is normal or faulty based upon the comparison.

Abstract: Select portions of product channel data collected by a product channel participant and stored in a data warehouse are periodically extracted based on a previously determined template. The extracted subset of product channel data is thereafter transformed so that the format of the data complies with that of the requesting enterprise. Once transformed, one or more rule sets is applied to the subset of transformed data to guarantee that the information complies with requirements set forth by the enterprise yet does not violate any disclosure rules of the product channel participant. Thereafter and on a scheduled basis, the transformed and validated data is delivered to a delivery server from which the enterprise can retrieve the data at its convenience.

Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.

Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.

Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.

Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.

Abstract: An error correction code system for a memory having parity columns of a memory array located within the memory array is provided. The parity columns are grouped together or distributed throughout the memory array. An embodiment includes a multiplexor circuit for selectively coupling only parity bits stored in the parity memory array to I/O circuitry, bypassing ECC logic circuitry and allowing the parity columns to be directly accessible, in a direct access mode or for selectively coupling the parity bits to ECC logic circuitry in an ECC mode.

Abstract: Select portions of product channel data collected by a product channel participant and stored in a data warehouse are periodically extracted based on a previously determined template. The extracted subset of product channel data is thereafter transformed so that the format of the data complies with that of the requesting enterprise. Once transformed, one or more rule sets is applied to the subset of transformed data to guarantee that the information complies with requirements set forth by the enterprise yet does not violate any disclosure rules of the product channel participant. Thereafter and on a scheduled basis, the transformed and validated data is delivered to a delivery server from which the enterprise can retrieve the data at its convenience.

Abstract: A merchant portal accessible by a user via the Internet searches for a product using typical search techniques. The merchant portal returns to the user a list of merchants in an identified geographic location. For each listed merchant, a token is created that associates the inquiry and the merchant. Once a token has been generated, financial transactions at the merchant are monitored for the time corresponding to the life of the token. When a transaction occurs at a merchant involving the user, a report is generated associating that sale with the inquiry. Based on the sale, a fee for directing the user to the merchant is generated.

Abstract: An error correction code system for a memory for improving performance and testability. The parity columns of the memory array can be positioned centrally within the array to minimize routing distance to ECC logic circuitry. The parity columns can be grouped together or distributed throughout the array to optimize performance. A multiplexor circuit can be included for selectively coupling only the parity bits stored in the parity memory array to I/O circuitry. Therefore, the parity columns can be directly tested, and testing of the ECC logic circuitry is facilitated.