Abstract: Systems and methods for placing capacitors between IC bumps and BGA balls are described. In one embodiment, the method may include placing a ball grid array (BGA) package or integrated circuit (IC) package on a printed circuit board (PCB) of an electronic device, and placing a capacitor between a first BGA ball and a second BGA ball of the BGA package and/or placing a capacitor between a first IC bump and a second IC bump of the IC package to maintain impedance of a power delivery network (PDN) of the BGA package or IC package below a target impedance.

Abstract: A substrate largely or entirely devoid of return current vias is disclosed. The substrate may include a first signal layer, a ground plane, a power plane and a second signal layer, each separated by a dielectric material. The ground plane and power plane together form a capacitor providing a return current path for the current in the signal layers.

Abstract: Systems and methods for routing of conductive traces in a printed circuit board are described. In one embodiment, the method may include routing a first trace in a first layer of a printed circuit board of a solid state drive, routing a second trace in a second layer of the printed circuit board, and routing the first trace and the second trace between a serializer/deserializer (SerDes) of a first controller of the solid state drive and a SerDes of a second controller of the solid state driver. In some cases, the first trace and the second trace may be configured to transmit differential signals to communicate data between the first controller and the second controller. In some embodiments, the second layer may be adjacent to the first layer.

Abstract: Systems and methods for tightly coupled differential vias are described. the storage system device includes a storage drive and a printed circuit board (PCB) of the storage drive. In some embodiments a first via is connected to a first trace routed on a first layer of the PCB, and a second via is connected to a second trace routed on the first layer of the PCB. In some cases, a distance between the first via and the second via is about 1.5 times or less a spacing between the first trace and the second trace.

Abstract: Systems and methods for placing capacitors between IC bumps and BGA balls are described. In one embodiment, the method may include placing a ball grid array (BGA) package or integrated circuit (IC) package on a printed circuit board (PCB) of an electronic device, and placing a capacitor between a first BGA ball and a second BGA ball of the BGA package and/or placing a capacitor between a first IC bump and a second IC bump of the IC package to maintain impedance of a power delivery network (PDN) of the BGA package or IC package below a target impedance.

Abstract: Systems and methods for tightly coupled differential vias are described. the storage system device includes a storage drive and a printed circuit board (PCB) of the storage drive. In some embodiments a first via is connected to a first trace routed on a first layer of the PCB, and a second via is connected to a second trace routed on the first layer of the PCB. In some cases, a distance between the first via and the second via is about 1.5 times or less a spacing between the first trace and the second trace.

Abstract: Systems and methods for maintaining a slew rate while loading flash memory dies are described. In one embodiment, the systems and methods may include placing one or more comparator circuits connectively between one or more channel controllers and a plurality of flash memory dies and maintaining a slew rate in relation to the one or more channel controllers writing data to a plurality of flash memory dies inside the solid state drive. In some cases, a hardware controller of a solid state drive may include the one or more channel controllers. In some cases, the plurality of flash memory dies may include at least one NAND die.

Abstract: Systems and methods for routing of conductive traces in a printed circuit board are described. In one embodiment, the method may include routing a first trace in a first layer of a printed circuit board of a solid state drive, routing a second trace in a second layer of the printed circuit board, and routing the first trace and the second trace between a serializer/deserializer (SerDes) of a first controller of the solid state drive and a SerDes of a second controller of the solid state driver. In some cases, the first trace and the second trace may be configured to transmit differential signals to communicate data between the first controller and the second controller. In some embodiments, the second layer may be adjacent to the first layer.

Abstract: Systems and methods for maintaining a slew rate while loading flash memory dies are described. In one embodiment, the systems and methods may include placing one or more comparator circuits connectively between one or more channel controllers and a plurality of flash memory dies and maintaining a slew rate in relation to the one or more channel controllers writing data to a plurality of flash memory dies inside the solid state drive. In some cases, a hardware controller of a solid state drive may include the one or more channel controllers. In some cases, the plurality of flash memory dies may include at least one NAND die.