Patents by Inventor Vinod Bussa
Vinod Bussa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11604757Abstract: Processing data in memory using a field programmable gate array by reading a first portion of a data set to a burst block having a first data format, transforming a sub-portion of the first portion, to an element block having a second data format, processing the sub-portion yielding a first results set, transforming the first results set to the first data format of the burst block, and writing the first results set to the burst block.Type: GrantFiled: July 17, 2019Date of Patent: March 14, 2023Assignee: International Business Machines CorporationInventors: Preetham M. Lobo, Gaurav Sulagodu Venkatagiri, Siva Sundar A, Vinod Bussa
-
Patent number: 11513983Abstract: Apparatuses, methods, program products, and systems are presented for interrupt migration in connection with migration of a logical partition.Type: GrantFiled: May 15, 2020Date of Patent: November 29, 2022Assignee: International Business Machines CorporationInventors: Timothy J. Schimke, Jesse Arroyo, Prathima Kommineni, Vinod Bussa
-
Patent number: 11188369Abstract: Apparatuses, methods, program products, and systems are presented for interrupt virtualization. An apparatus includes an adapter module that detects a switch from a first physical input/output (“I/O”) adapter associated with a logical partition to a second physical I/O adapter associated with the logical partition. The apparatus includes an interrupt module that updates one or more I/O interrupt management structures for the logical partition so that the logical partition receives I/O interrupt information from the second physical I/O adapter and not the first physical I/O adapter without the logical partition being aware of the switch to the second I/O adapter. The apparatus includes an abstraction module that updates physical device information at a hypervisor for the logical partition to reflect the switch to the second physical I/O device.Type: GrantFiled: November 26, 2018Date of Patent: November 30, 2021Assignee: International Business Machines CorporationInventors: Jesse Arroyo, Prathima Kommineni, Timothy Schimke, Vinod Bussa
-
Publication number: 20210357342Abstract: Apparatuses, methods, program products, and systems are presented for interrupt migration in connection with migration of a logical partition.Type: ApplicationFiled: May 15, 2020Publication date: November 18, 2021Inventors: Timothy J. Schimke, Jesse Arroyo, Prathima Kommineni, Vinod Bussa
-
Publication number: 20210019280Abstract: Processing data in memory using a field programmable gate array by reading a first portion of a data set to a burst block having a first data format, transforming a sub-portion of the first portion, to an element block having a second data format, processing the sub-portion yielding a first results set, transforming the first results set to the first data format of the burst block, and writing the first results set to the burst block.Type: ApplicationFiled: July 17, 2019Publication date: January 21, 2021Inventors: Preetham M. Lobo, Gaurav Sulagodu Venkatagiri, Siva Sundar A, Vinod Bussa
-
Publication number: 20200167176Abstract: Apparatuses, methods, program products, and systems are presented for interrupt virtualization. An apparatus includes an adapter module that detects a switch from a first physical input/output (“I/O”) adapter associated with a logical partition to a second physical I/O adapter associated with the logical partition. The apparatus includes an interrupt module that updates one or more I/O interrupt management structures for the logical partition so that the logical partition receives I/O interrupt information from the second physical I/O adapter and not the first physical I/O adapter without the logical partition being aware of the switch to the second I/O adapter. The apparatus includes an abstraction module that updates physical device information at a hypervisor for the logical partition to reflect the switch to the second physical I/O device.Type: ApplicationFiled: November 26, 2018Publication date: May 28, 2020Inventors: Jesse Arroyo, Prathima Kommineni, Timothy Schimke, Vinod Bussa
-
Patent number: 10261917Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.Type: GrantFiled: December 22, 2017Date of Patent: April 16, 2019Assignee: International Business Machines CorporationInventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
-
Patent number: 10169181Abstract: A transactional memory test tests a transactional memory system on a computer processor. A test case with a transactional memory test is constructed such that the transactional memory test proceeds further in the transaction mode if the transaction is successful. In contrast, if there is a failure of the transaction, then the transactional memory test is executed in the non-transaction state. The transactional memory test stresses both transaction success and transaction failure cases of the processor for more efficient validation of the computer processor. Also, when checking the correctness of the test case the correct result remains the same whether the transaction passes or fails to simplify verification.Type: GrantFiled: September 15, 2016Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
-
Publication number: 20180121365Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.Type: ApplicationFiled: December 22, 2017Publication date: May 3, 2018Inventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
-
Publication number: 20180074926Abstract: A transactional memory test tests a transactional memory system on a computer processor. A test case with a transactional memory test is constructed such that the transactional memory test proceeds further in the transaction mode if the transaction is successful. In contrast, if there is a failure of the transaction, then the transactional memory test is executed in the non-transaction state. The transactional memory test stresses both transaction success and transaction failure cases of the processor for more efficient validation of the computer processor. Also, when checking the correctness of the test case the correct result remains the same whether the transaction passes or fails to simplify verification.Type: ApplicationFiled: September 15, 2016Publication date: March 15, 2018Inventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
-
Patent number: 9892060Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.Type: GrantFiled: December 2, 2015Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
-
Patent number: 9720845Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.Type: GrantFiled: January 16, 2017Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
-
Patent number: 9697138Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.Type: GrantFiled: January 16, 2017Date of Patent: July 4, 2017Assignee: International Business Machines CorporationInventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
-
Publication number: 20170161208Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.Type: ApplicationFiled: January 16, 2017Publication date: June 8, 2017Inventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
-
Publication number: 20170161192Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.Type: ApplicationFiled: December 2, 2015Publication date: June 8, 2017Inventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
-
Publication number: 20170161209Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.Type: ApplicationFiled: January 16, 2017Publication date: June 8, 2017Inventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
-
Patent number: 9594680Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.Type: GrantFiled: August 25, 2016Date of Patent: March 14, 2017Assignee: International Business Machines CorporationInventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
-
Patent number: 8019566Abstract: A system and method for using a single test case to test each sector within multiple congruence classes is presented. A test case generator builds a test case for accessing each sector within a congruence class. Since a congruence class spans multiple congruence pages, the test case generator builds the test case over multiple congruence pages in order for the test case to test the entire congruence class. During design verification and validation, a test case executor modifies a congruence class identifier (e.g., patches a base register), which forces the test case to test a specific congruence class. By incrementing the congruence class identifier after each execution of the test case, the test case executor is able to test each congruence class in the cache using a single test case.Type: GrantFiled: September 11, 2007Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Batchu Naga Venkata Satyanarayana
-
Patent number: 7966521Abstract: A test case manager selects a first test case and a second test case from a plurality of test cases. The test case manager provides the first test case to a first processor and provides the second test case to a second processor. As such, the first processor executes the first test case and the second processor executes the second test case. After the execution, the test case manager loads the first test case onto the second processor and loads the second test case onto the first processor. In turn, the first processor executes the second test case and the second processor executes the first test case.Type: GrantFiled: July 14, 2008Date of Patent: June 21, 2011Assignee: International Business Machines CorporationInventors: Vinod Bussa, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor
-
Patent number: 7669083Abstract: A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.Type: GrantFiled: September 11, 2007Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Sampan Arora, Sandip Bag, Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Batchu Naga Venkata Satyanarayana, Shiraz Mohammad Zaman