Patents by Inventor Vinod K. Jain

Vinod K. Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8378725
    Abstract: A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current converter converts a control voltage to a first current. A current-controlled oscillator generates the oscillator signal based on the first current. A dual charge pump circuit generates first and second charge pump currents having a predetermined ratio, based on a second current generated by a current mirror circuit and an error (feedback) signal. An active loop filter generates the control voltage based on the first and second charge pump currents. The active loop filter includes an input capacitance that varies with a variation in the predetermined ratio of the charge pump currents. The active loop filter also includes a transconductance stage having a transconductance that varies based on a third current generated by a current mirror circuit. The PLL bandwidth is independent of PVT variations and dependent only on the frequency of the input reference signal.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: February 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Krishna Thakur, Deependra K. Jain, Vinod K. Jain
  • Patent number: 8354866
    Abstract: A start-up circuit for a PLL includes a phase-frequency detector (PFD), one or more logic gates, a flip-flop and a false detection circuit. The false detection circuit includes a set of series connected flip-flops. The PFD receives a reference signal and a feedback signal. The PFD compares the frequency of a reference signal with that of a feedback signal. If the frequency of the reference signal is greater than the frequency of the feedback signal then a start-up signal is generated and transmitted to the PLL. The PLL increases the frequency of the feedback signal until it is greater than the frequency of the reference signal. The generation of the start-up signal is halted when the frequency of the feedback signal is greater than the frequency of the reference signal.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: January 15, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vinod K. Jain, Anand K. Sinha, Sanjay Kumar Wadhwa
  • Publication number: 20120235718
    Abstract: A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current converter converts a control voltage to a first current. A current-controlled oscillator generates the oscillator signal based on the first current. A dual charge pump circuit generates first and second charge pump currents having a predetermined ratio, based on a second current generated by a current mirror circuit and an error (feedback) signal. An active loop filter generates the control voltage based on the first and second charge pump currents. The active loop filter includes an input capacitance that varies with a variation in the predetermined ratio of the charge pump currents. The active loop filter also includes a transconductance stage having a transconductance that varies based on a third current generated by a current mirror circuit. The PLL bandwidth is independent of PVT variations and dependent only on the frequency of the input reference signal.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 20, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Krishna THAKUR, Deependra K. JAIN, Vinod K. JAIN
  • Publication number: 20120133405
    Abstract: A start-up circuit for a PLL includes a phase-frequency detector (PFD), one or more logic gates, a flip-flop and a false detection circuit. The false detection circuit includes a set of series connected flip-flops. The PFD receives a reference signal and a feedback signal. The PFD compares the frequency of a reference signal with that of a feedback signal. If the frequency of the reference signal is greater than the frequency of the feedback signal then a start-up signal is generated and transmitted to the PLL. The PLL increases the frequency of the feedback signal until it is greater than the frequency of the reference signal. The generation of the start-up signal is halted when the frequency of the feedback signal is greater than the frequency of the reference signal.
    Type: Application
    Filed: November 25, 2010
    Publication date: May 31, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Vinod K. JAIN, Anand K. Sinha, Sanjay Kumar Wadhwa
  • Patent number: 5361477
    Abstract: A method for extruding metals and alloys, particularly difficult-to-work high temperature alloys, is described which comprises inserting a billet of the metal or alloy into an extrusion can, heating the canned billet to a temperature in a temperature range in which the ductility of the billet material is substantially maximum, cooling the canned billet sufficiently to establish a preselected temperature difference between the billet and can at which the difference between the flow stress of the billet material and the flow stress of the can material is substantially minimum, and extruding the canned billet to preselected shape.
    Type: Grant
    Filed: March 10, 1994
    Date of Patent: November 8, 1994
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Sheldon L. Semiatin, Venkat Seetharaman, Robert L. Goetz, Vinod K. Jain