Abstract: A circuit for rapidly rotating a digital image through 90 or 270 degrees utilizing memory implemented from ordinary 4-bit wide memory devices. This pipelined circuit transfers the image through a page buffer and a band buffer in a series of memory accessing, shining and reordering steps which converts all vertical lines to horizontal lines and all horizontal lines to vertical lines without requiring the use of a parallel to serial conversion.

Abstract: A circuit for addressing a random access memory (RAM) and for rotating an image by reading it into and then out from a page buffer, where all transfers, whether by column or row, are performed substantially in a fast page mode in which the same row address is maintained from one access to the next. The column address lines of RAM devices are connected to the 5 or 6 least significant bits of the vertical and horizontal address counters of the image, and the row address lines are connected to the remaining most significant bits of the vertical and horizontal counters of the image. Therefore, whether the system is accessing the image data in the vertical or horizontal direction, there will be at least 31 fast page mode accesses for every one slow access, and the average speed of transfers in either direction will approximate the fast page mode speed.

Abstract: An algorithm for rotating an image 90 degrees starts with an array or r rows and c columns of pixels. Each column of the pixel array is partitioned into words of w pixels each, and the rows, the columns, the words in each column, and the pixels in each word of the pixel array are all numbered starting at zero. Let v= r/w , where r/w is the smallest integer greater than or equal to r/w. Similarly, let h- c/w . The algorithm stores words of the original pixel array into a linear word organized memory as follows: it circular right-shifts each word i of column j by (j)mod w pixel positions and then writes in parallel this modified word into word address vj+i of the memory.

Abstract: A predictor bit pattern comprising selected bits of the current and previous raster scan lines and a method of predicting a plurality of bits per clock are disposed. Generally, a predictor is used prior to the encoding of data to increase the compression. The current bit in a bit stream is compared to the predicted value and a one is output when the two values are not equal. An efficient predictor will reduce the number of ones in a bit stream, which increases the zero run lengths and increases the efficiency of a run length encoding system. The described bit pattern contains bits close to the current bit to efficiently predict text data, bits distant from the current bit to efficiently predict halftone data, and ignores a plurality of intermediate bits to reduce hardware costs. A two step process is also described to allow a plurality of bits to be predicted in parallel.

Abstract: A circuit to encode image data. The circuit receives image data in four bit nibbles which are either all-zero nibbles or terminating nibbles containing at least one non-zero bit. The circuit output is a series of code words, each a multiple of four bits and up to twenty-four bits long, packed into eight bit output words. Each code word contains a first part containing a run length specifying the number of received all-zero nibbles and a second part specifying the bit pattern of the terminating nibble. The circuit uses PROMs for the look-up and control elements and a pipeline of registers to allow high speed operation.