Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.

Abstract: Disclosed are processes of making solutions of metal alcoholates in their corresponding alcohols using an electrolytic process. In one embodiment, sodium methylate in methanol is made from methanol and sodium hydroxide solution. The sodium hydroxide solution is placed in the anolyte compartment and the methanol is placed in the catholyte compartment, and the two compartments are separated by a ceramic membrane that selectively transports sodium under the influence of current. In preferred embodiments, the process is cost-effective and not environmentally harmful.

Abstract: Disclosed are processes of making solutions of metal alcoholates in their corresponding alcohols using an electrolytic process. In a preferred embodiment, sodium methylate in methanol is made from methanol and sodium hydroxide solution. The sodium hydroxide solution is placed in the anolyte compartment and the methanol is placed in the catholyte compartment, and the two compartments are separated by a ceramic membrane that selectively transports sodium under the influence of current. In preferred embodiments, the process is cost-effective and not environmentally harmful.

Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.

Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.

Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.

Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.

Abstract: Design rule checking (DRC) can be applied to a mask layout using a shape-based system. A shape includes a set of associated edges in a specified configuration. Design rules can then be based on various shapes, advantageously enabling efficient formulation and precise application of design rules. A concurrent processing methodology can be used to minimize processing overhead during this rule application. Design rules can also be incorporated into a lookup table (LUT) to further reduce DRC runtime by substantially minimizing the number of times a design rule must actually be calculated. A LUT can also improve DRC runtime for edge-based, concurrent processing DRC systems. A DRC system can also be connected to a network across which design rules and mask layout data files can be accessed and retrieved.