Abstract: An interface unit for data transfer between a processor bus and an ISDN-based bus is disclosed. The ISDN-based bus is an IOM-2 bus. The interface unit enables access to all available IOM-2 slots, thereby increasing data transfer rate between the processor and IOM-2 buses.

Abstract: An interface unit for data transfer between a processor bus and an ISDN-based bus is disclosed. The ISDN-based bus is an IOM-2 bus. The interface unit enables access to all available IOM-2 slots, thereby increasing data transfer rate between the processor and IOM-2 buses.

Abstract: A communication device has a microcontroller for high-speed data handling. A terminal-specific function unit separated from the microcontroller performs all control functions for the user interface devices, preferably keypad scanning, LCD control, and LED control. The function of the circuit block is preferably hard-wired. The circuit block connects to the microcontroller via the microcontroller bus. The microcontroller is freed from user interface control functions and is concentrated on data handling.

Abstract: A keypad arrangement is disclosed comprising a scanning unit (30) having a certain number of port line terminals (1 to 11) and a number of sensor cells (21) arranged in half-matrix structure having rows (23) and columns (22) whereby the number of columns (22) and the number of rows (23) each are less than the number of port line terminals. In comparison to normal detection systems, the given detection system allows a significant reduction of the port line terminals required to scan a given number of sensor cells. The device described is preferably applicable in communication devices.

Abstract: The present invention relates to a communication circuit arrangement (1) providing a testing functionality. A switch (10) couples internal circuit nodes of a transmission path (2) and a receiver path (3) of an interface communication circuit (1), thereby providing a test signal loop. By feeding a test signal (A) into an input terminal (11) of a transmission path (2) and comparing this original signal (A) with a received signal (B) from output terminal (14) of receiver path (3), functional faults of the circuit are revealed at early development stages. The test method is preferably applicable in communication devices.

Abstract: A logic device includes a RAM and control apparatus (10). The control apparatus (10) is adapted to receive input signals (6) from a processor and the control apparatus (10) is also adapted to be coupled to the RAM to send signals to the RAM in response to the input signals (6). The control apparatus (10) includes a data generator (3) and the data generator generates a test bit pattern which is dependent on the received input signals (6).