Patents by Inventor Vinod Purayath
Vinod Purayath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9552991Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench.Type: GrantFiled: April 30, 2014Date of Patent: January 24, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Akira Matsudaira, James Kai, Yuan Zhang, Vinod Purayath, Donovan Lee
-
Patent number: 9230971Abstract: A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.Type: GrantFiled: January 28, 2015Date of Patent: January 5, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Donovan Lee, Vinod Purayath, James Kai, George Matamis
-
Publication number: 20150318295Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating insulating layers and control gate films over a major surface of a substrate. Each of the control gate films includes a middle layer located between a first control gate layer and a second control gate layer, the middle layer being a different material from the first and second control gate layers and from the insulating layers. The method also includes forming a front side opening in the stack, and forming a blocking dielectric, at least one charge storage region, a tunnel dielectric and a semiconductor channel in the front side opening in the stack.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Applicant: SanDisk Technologies, Inc.Inventors: James Kai, Vinod Purayath, Donovan Lee, Akira Matsudaira
-
Publication number: 20150318298Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Applicant: SanDisk Technologies, Inc.Inventors: Akira Matsudaira, James Kai, Yuan Zhang, Vinod Purayath, Donovan Lee
-
Patent number: 9165940Abstract: A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers.Type: GrantFiled: November 12, 2014Date of Patent: October 20, 2015Assignee: SANDISK TECHNOLOGIES INC.Inventors: Henry Chien, Johann Alsmeier, George Samachisa, Henry Chin, George Matamis, Yuan Zhang, James Kai, Vinod Purayath, Donovan Lee
-
Publication number: 20150137208Abstract: A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.Type: ApplicationFiled: January 28, 2015Publication date: May 21, 2015Inventors: Donovan Lee, Vinod Purayath, James Kai, George Matamis
-
Patent number: 9029936Abstract: A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.Type: GrantFiled: December 7, 2012Date of Patent: May 12, 2015Assignee: SanDisk Technologies Inc.Inventors: Vinod Purayath, George Samachisa, George Matamis, James Kai, Yuan Zhang
-
Patent number: 8987802Abstract: A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.Type: GrantFiled: February 28, 2013Date of Patent: March 24, 2015Assignee: SanDisk Technologies Inc.Inventors: Donovan Lee, James Kai, Vinod Purayath, George Matamis, Steven J. Radigan
-
Publication number: 20150072488Abstract: A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers.Type: ApplicationFiled: November 12, 2014Publication date: March 12, 2015Inventors: Henry Chien, Johann Alsmeier, George Samachisa, Henry Chin, George Matamis, Yuan Zhang, James Kai, Vinod Purayath, Donovan Lee
-
Patent number: 8969153Abstract: A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.Type: GrantFiled: July 1, 2013Date of Patent: March 3, 2015Assignee: SanDisk Technologies Inc.Inventors: Donovan Lee, Vinod Purayath, James Kai, George Matamis
-
Patent number: 8928061Abstract: A monolithic three dimensional NAND string includes a semiconductor channel located over a substrate, a plurality of control gates extending substantially parallel to the major surface of the substrate including a first control gate located in a first device level and a second control gate located in a second device level located over the substrate and below the first device level, a charge storage material including a silicide layer located in the first device level and in the second device level, a blocking dielectric located between the charge storage material and the plurality of control gates, and a tunnel dielectric located between the charge storage material and the semiconductor channel. The tunnel dielectric has a straight sidewall, portions of the blocking dielectric have a clam shape, and each of the plurality of control gates is located at least partially in an opening in the clam-shaped portion of the blocking dielectric.Type: GrantFiled: February 26, 2014Date of Patent: January 6, 2015Assignee: SanDisk Technologies, Inc.Inventors: Henry Chien, Johann Alsmeier, George Samachisa, Henry Chin, George Matamis, Yuan Zhang, James Kai, Vinod Purayath, Donovan Lee
-
Publication number: 20150001607Abstract: A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.Type: ApplicationFiled: July 1, 2013Publication date: January 1, 2015Applicant: SanDisk Technologies, Inc.Inventors: Donovan LEE, Vinod PURAYATH, James KAI, George MATAMIS
-
Patent number: 8822288Abstract: A method of fabricating a memory device includes providing multiple coatings of nanodots on a tunnel dielectric layer to form a floating gate layer having a high nanodot density. The memory device may have a nanodot-containing floating gate layer with a density greater than 4×1012 dots/cm2. Further methods include forming an oxidation barrier layer, such as a silicon nitride shell, over a surface of the nanodots, and depositing a dielectric material over the nanodots to form a floating gate layer.Type: GrantFiled: December 7, 2012Date of Patent: September 2, 2014Assignee: Sandisk Technologies Inc.Inventors: Vinod Purayath, George Samachisa, George Matamis, James Kai, Yuan Zhang
-
Patent number: 8823075Abstract: Methods of fabricating a memory device include forming a tunnel oxide layer over a memory cell area of a semiconductor substrate, forming a floating gate layer over the tunnel oxide layer in the memory cell area, the floating gate layer comprising a plurality of nanodots embedded in a dielectric material, forming a blocking dielectric layer over the floating gate layer in the memory cell area, removing portions of the blocking dielectric layer, the floating gate layer, the tunnel oxide layer, and the semiconductor substrate in the memory cell area to form a first plurality of isolation trenches, and forming isolation material within the first plurality of isolation trenches.Type: GrantFiled: November 30, 2012Date of Patent: September 2, 2014Assignee: SanDisk Technologies Inc.Inventors: Vinod Purayath, James Kai, Yuan Zhang, Donovan Lee, George Matamis
-
Publication number: 20140239365Abstract: A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: Donovan Lee, James Kai, Vinod Purayath, George Matamis, Steven J. Radigan
-
Publication number: 20140175530Abstract: A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers.Type: ApplicationFiled: February 26, 2014Publication date: June 26, 2014Applicant: SanDisk Technologies Inc.Inventors: Henry Chien, Johann Alsmeier, George Samachisa, Henry Chin, George Matamis, Yuan Zhang, James Kai, Vinod Purayath, Donovan Lee
-
Publication number: 20140151778Abstract: Methods of fabricating a memory device include forming a tunnel oxide layer over a memory cell area of a semiconductor substrate, forming a floating gate layer over the tunnel oxide layer in the memory cell area, the floating gate layer comprising a plurality of nanodots embedded in a dielectric material, forming a blocking dielectric layer over the floating gate layer in the memory cell area, removing portions of the blocking dielectric layer, the floating gate layer, the tunnel oxide layer, and the semiconductor substrate in the memory cell area to form a first plurality of isolation trenches, and forming isolation material within the first plurality of isolation trenches.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Applicant: SanDisk Technologies, Inc.Inventors: Vinod Purayath, James Kai, Yuan Zhang, Donovan Lee, George Matamis
-
Publication number: 20140001535Abstract: A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.Type: ApplicationFiled: December 7, 2012Publication date: January 2, 2014Applicant: SanDisk Technologies, Inc.Inventors: Vinod Purayath, George Samachisa, George Matamis, James Kai, Yuan Zhang
-
Publication number: 20140001533Abstract: A method of fabricating a memory device includes providing multiple coatings of nanodots on a tunnel dielectric layer to form a floating gate layer having a high nanodot density. The memory device may have a nanodot-containing floating gate layer with a density greater than 4×1012 dots/cm2. Further methods include forming an oxidation barrier layer, such as a silicon nitride shell, over a surface of the nanodots, and depositing a dielectric material over the nanodots to form a floating gate layer.Type: ApplicationFiled: December 7, 2012Publication date: January 2, 2014Applicant: SANDISK TECHNOLOGIES, INC.Inventors: Vinod Purayath, George Samachisa, George Matamis, James Kai, Yuan Zhang
-
Patent number: 8455939Abstract: A NAND device including a source, a drain and a channel located between the source and drain. The NAND device also includes a plurality of floating gates located over the channel and a plurality of electrically conducting fins. Each of the plurality of electrically conducting fins is located over one of the plurality of floating gates. The plurality of electrically conducting fins include a material other than polysilicon. The NAND device also includes a plurality of control gates. Each of the plurality of control gates is located adjacent to each of the plurality of floating gates and each of the plurality of electrically conducting fins.Type: GrantFiled: December 21, 2010Date of Patent: June 4, 2013Assignee: SanDisk Technologies Inc.Inventors: Johann Alsmeier, Vinod Purayath, James Kai, George Matamis