Abstract: A lossless data compressor of an aspect includes a first lossless data compressor circuitry coupled to receive input data. The first lossless data compressor circuitry is to apply a first lossless data compression approach to compress the input data to generate intermediate compressed data. The apparatus also includes a second lossless data compressor circuitry coupled with the first lossless data compressor circuitry to receive the intermediate compressed data. The second lossless data compressor circuitry is to apply a second lossless data compression approach to compress at least some of the intermediate compressed data to generate compressed data. The second lossless data compression approach different than the first lossless data compression approach. Lossless data decompressors are also disclosed, as are methods of lossless data compression and decompression.

Abstract: Methods and apparatus for dynamic offline end-to-end packet processing based on traffic class. An end-to-end connection is set up between an application on a client including a processor and host memory and an application on a remote server. An offline packet buffer is allocated in host memory. While the processor and/or a core on with the client application is executed is in a sleep state, the client is operated in an interrupt-less and polling-less mode as applied to a predetermined traffic class. Under the mode, a Network Interface Controller (NIC) at the client receives network traffic from the remote server and determines whether the network traffic is associated with the predetermined traffic class. When it is, the NIC writes packet data extracted from the network traffic to an offline packet buffer. Descriptors are generated and provided to the NIC to inform the NIC of the location and size of the offline packet buffer.

Abstract: Methods and apparatus relating to an efficient implementation of ZUC authentication are described. In one embodiment, a processor computes a tag update, based at least in part on stored data, for an authentication operation. The tag update is computed by replacing a ‘for’ loop with a carry-less multiply operation. Other embodiments are also claimed and disclosed.

Abstract: In one embodiment, a method includes: receiving, in an edge platform, a plurality of messages from a plurality of edge devices coupled to the edge platform, the plurality of messages comprising metadata including priority information and granularity information; extracting at least the priority information from the plurality of messages; storing the plurality of messages in entries of a pending request queue according to the priority information; selecting a first message stored in the pending request queue for delivery to a destination circuit; and sending a message header for the first message to the destination circuit via at least one interface circuit, the message header including the priority information, and thereafter sending a plurality of packets including payload information of the first message to the destination circuit via the at least one interface circuit. Other embodiments are described and claimed.

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.

Abstract: An apparatus may include an accelerator and a processor. The processor may receive an input string targeting a data buffer comprising a plurality of strings. The processor may receive, from the accelerator, a fixed-length data buffer based on the data buffer, respective ones of a plurality of entries of the fixed-length data buffer based on respective ones of the strings. The processor may receive, from the accelerator, a plurality of streams, respective ones of the plurality of streams to comprise a portion of respective entries in the fixed-length data buffer. The processor may generate, based on the input string, a plurality of target portions of the input string. The processor may receive, from the accelerator, indexes of the plurality of streams based on respective target portions of the input string matching respective entries of the plurality of streams. The processor may aggregate the indexes received from the accelerator.

Abstract: A method is described. The method includes receiving a request. The method includes allocating and/or configuring hardware to execute the request in accordance with an energy related input specified by a sender of the request. The method includes causing execution of the request in accordance with the energy related input.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to generate and manage a firewall policy. An example includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to determine whether an operation is allowed to pass between a first component on a system-on-chip (SoC) and a second component on the SoC, detect an interconnect between the first component on the SoC and the second component on the SoC, cause the interconnect to filter the operation based on the determination of whether the operation is allowed to pass between the first component and the second component, and transmit a request to filter the operation based on the determination of whether the operation is allowed to pass between the first component and the second component.

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

Abstract: An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused addition and subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results. Other embodiments are disclosed and claimed.

Abstract: An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused multiple multiplication and addition-subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused multiple multiplication and addition-subtraction indicated by the opcode on four or more arguments indicated by the retrieved data to produce one or more results. Other embodiments are disclosed and claimed.

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

Abstract: Dynamic resource reconfiguration based on workload semantics and behavior. A controller may receive, from a core network, a request for an end-to-end managed connection, the end-to-end managed connection for an application executing on a server and an application executing on a client device, where the client device is coupled to the controller via a radio access network (RAN). The controller may determine a policy for the end-to-end managed connection. The controller may apply one or more parameters of the policy to the end-to-end managed connection.

Abstract: Apparatus and method for performing vector packed concatenate and shift of portions of quadwords are described herein. An apparatus embodiment includes decoder circuitry to decode a first instruction and execution circuitry to execute the decoded instruction. The execute circuitry includes concatenation circuitry to concatenate a first field from each of a first plurality of data elements with a second field from a corresponding data element of the second plurality of data elements to generate a plurality of concatenated results, and shift circuitry to shift each of the plurality of concatenated results by a number of bit positions specified by a corresponding shift value to generate a plurality of shifted results, wherein a select plurality of bits from each of the plurality of shifted results is stored in a corresponding data element position of a destination register.

Abstract: Apparatus and method for detecting a constant data block are described herein. An apparatus embodiment includes compression circuitry to perform compression operations on a memory block; constant detection circuitry to, concurrently with performance of the compression operations on the memory block, determine that the memory block is a constant data block comprised of only repeat instances of a constant value; and controller circuitry to associate a first indication with the memory block based on the determination, the first indication usable for controlling whether to abort the compression operations or whether to discard a compressed memory block generated from the compression operations.

Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.

Abstract: An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, in one embodiment, a processor comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.

Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device includes circuitry to provide access to an accelerator device on a second platform to perform a workload in response to communication with a device driver executed by a first platform. In some examples, the first platform and second platform are connected by a network and wherein the accelerator device satisfies a selection criteria and wherein the selection criteria comprises a device type. In some examples, the accelerator device on the second platform is accessible to an application via the device driver.